05-19-2009 07:26 PM - edited 06-11-2009 08:38 PM
I wrote a code for convolution in vhdl. I could simulate and synthesize it but the number of number of IOBs used exceeds the number available.
05-19-2009 10:26 PM
IOB is related to the I/O pins of the FPGA you are using. Where as LUTs / Slices/CLB of the FPGA is related to the code.
I have never tried the code of Convolution. But I am sure in XC3S200 you can easily carry out the code of convolution as per datasheet the resources avialable in XC3S200 is not bad.
Device - SystemGates - LogicCells - TotalCLBs - DistributedRAM - BlockRAM - Multipliers - DCMs - MaxUser I/O - MaxDiff I/O Pairs
XC3S200 - 200K - 4,320 - 480 - 30K - 16K - 12 - 4 - 173 - 76
05-19-2009 11:54 PM
please provide us with the entity of your source code and the package type of your FPGA.
The number of IOBs needed depends on the input and output signals you have defined in the entity.
Depending on the used IC package you have a different number of IOBs available for the same type of FPGA.
So take a look at both and remember:
integers use 32bits = 32IOBs;
unsigned, signed and xxx_vectors use as many IOBs as they have bits defined (e.g. 7 downto 0 = 8 IOBs)
And if you are doing arithmetic in FPGAS don't forget to downsize the bitnumber in your results:
e.g. multiplying two 8 bit numbers results in 16 bits, but you have to decide wisely wether to keep these bits
or to use just the upper 8 bits and either round or truncenate the rest.
Of course your result is then numerically attenuated by 256. But that's just a constant you have to keep in mind when dealing with these numbers.
Remember when doing DSP: There is no such thing as a 128 bit DAC available on the market. ;-)
Have a nice synthesis
05-20-2009 11:27 AM - edited 07-01-2009 05:46 PM
Thanks for your reply.
I will use Spartan 3. I used input sequence and window of lengths 9 with each being 4bits long, eventually I would perform convolution on image pixels(8 bits). I think all the values are read simultaneous, is it not possible to read inputs in sequential order? Here is my code:
05-20-2009 12:52 PM
entity test3 is
port( a : in arrayI;
k : in arrayK;
clock : in std_logic;
b : out arrayO);
package Package_Array is
subtype bit8 is std_logic_vector(7 downto 0);
subtype bit16 is std_logic_vector(15 downto 0);
subtype bit4 is std_logic_vector(3 downto 0);
type arrayI is array(9 downto 1) of bit4;
type arrayK is array(9 downto 1) of bit4;
type arrayO is array(17 downto 1) of bit8;
entity test3 is
a : in arrayI; --------------- 9 Bit x 4 Bit = 36 IOS Required
k : in arrayK; -------------- 9 Bit x 4 Bit = 36 IOS Required
clock : in std_logic;-------1 Bit = 1 IOS Required
b : out arrayO ------------17 Bit x 8Bit = 136 IOS Required
There for total IOS required in your project = 36 + 36 + 1 + 136 = 209
Where as for XC3S200 maximum number of IOS avialable is 173 (Check out for the package FTG256 it may be even less). That is the reason you are getting the error message.
05-22-2009 04:56 PM
05-22-2009 10:24 PM
You can use Serial in Parallel Out Shift Registers at a higher Clk speed
05-26-2009 04:34 AM
Now that Shantanu showed you how to calculate the pin count, you are right to ask about serializing the input data.
Well, there are several ways to do that.
1) N Inputs bit-serial
2) one Input Byte/Word-Serial
In the end it depends on the data source you want to connect to the FPGA. What is it?
A video RAM or video decoder chip or a camera?
Let's assume you have a N-Bit Port on your source.
Then you can shift the data into a register pipeline of N-Bits width and the required length for your algorithm.
Once the pipeline is filled with the data you can access all registers at the same time to calculate your result.
You save a lot of pins and need just some Flipflops for storage purposes.
Maybe a state machine (FSM) to control the dataflow and calculations would be useful.
So, what has to be considered for an FPGA Design:
1st: Know your hardware. What interfaces are to be connected with your FPGA. What ressources does the FPGA have ... etc.
2nd: Know your algorithms. How to prepare the incoming data to be fed into the algorithms. How to structure the algorithm to work efficiently on hardware ... etc.
3rd: Keep in control. A FSM or small processor (e.g. picoblaze) is almost always neccessary or, at least, useful to manage the dataflow.
Now take some time to think about your design and
have a nice synthesis
11-04-2012 11:16 PM