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1,150 Views
Registered: ‎03-22-2018

core dumped while running synthesis

Hi,

 

I'm trying to  run synthesis with quite a large RTL design.

  Target device is :VU9P

  Vivado version: v2017.4 (64-bit)

  Linux version: Red Hat Enterprise Linux Server release 7.4 (Maipo)

 

After ~9 hours running, it got core dumped after "Start Final Netlist Cleanup" with the following messages:

---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
tcmalloc: large alloc 2086715392 bytes == 0x4ee04e000 @ 0x7f5968c1b63f 0x7f592a22e640
tcmalloc: large alloc 2080178176 bytes == 0x4f7d02000 @ 0x7f5968c1b63f 0x7f592a22e640
tcmalloc: large alloc 2074705920 bytes == 0x4f7cea000 @ 0x7f5968c1b63f 0x7f592a4d728f
/opt/Xilinx/Vivado/2017.4/bin/loader: line 194: 23665 Segmentation fault (core dumped) "$RDI_PROG" "$@"
Parent process (pid 23665) has died. This helper process will now exit

 

Any suggestion for how to solve this issue?

 

Thanks,

Cindy

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2 Replies
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Mentor
Mentor
1,135 Views
Registered: ‎02-24-2014

Three possibilities come to mind..    

 

1.  your computer ran out of ram and it crashed trying to allocate more from the heap.   Probably not likely.

 

2.  the code contains some blocks that need huge amounts of memory..   the final messages indicate a request for 2+ Gbytes of memory, which is a LOT.    Can you divide the design hierarchy into pieces, and compile the pieces separately?  This is a crucial test, and also a possible workaround.   A very large design can be knit together from multiple netlists.

 

3.  Vivado 2017.4 has a bug, and your code slams into the bug.   Other versions of Vivado may or may not behave the same.

 

Diagnostic procedure:   Divide and conquer.    Break up the design into smaller pieces and test synthesis on the pieces.  Save the results as design checkpoints, so you can attempt to load them into the full design.  

 

 

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
1,109 Views
Registered: ‎07-21-2014

cindywang@dinoplus.ai

 

Can you try to invoke Vivado tool with command "vivado -stack 2000" and then launch the synthesis run?

 

Thanks

Anusheel

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