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Visitor
Visitor
11,909 Views
Registered: ‎02-11-2013

create RPM macros

I tried to create an RPM macro, working throug all the Xilinx documentation the last days.

My simple test program looks the following:

 

module RPM_test( input clocka, input clockb, output [1:0]outa, output [1:0]outb );

     tog tog0( clocka, outa[1:0] );

     tog tog1( clockb, outb[1:0] );
endmodule

 

// the module which should get the RPM:

 

module tog ( input clock, output reg [1:0]out );

 

    always@(posedge clock )

     begin

        out[0] <= !out[1];

        out[1] <= !out[0];

     end

 

endmodule

 

Now I have to create the constraints to get the RPM:

In UCF file:

    INST "tog1/out_0" U_SET=tog | RLOC=X0Y0;
    INST "tog1/out_1" U_SET=tog | RLOC=X7Y7;
    INST "tog1/out_0" U_SET=cde | RLOC=X0Y0;
    INST "tog1/out_1" U_SET=cde | RLOC=X1Y1;

 

This works fine, but it is not an RPM but constraints for the full design.

When I have a macro with hundreds of elements instantiated a hundred times, there is a problem.

 

For this problem the HU_SET command should work. So next step:

    INST "tog1/out_0" HU_SET=tog | RLOC=X0Y0;
    INST "tog1/out_1" HU_SET=tog | RLOC=X7Y7;

 

As expected this works only for the module tog1, because an absolute path to the elements is referenced.

 

I do not see a way to reference the elements inside the macro, independent from its position in the hirarchy.

Could someone help ?

 

 

 

 

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Xilinx Employee
Xilinx Employee
11,900 Views
Registered: ‎09-20-2012

Hi,

 

How about specifying the RLOC attributes in the RTL files?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor
Visitor
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Registered: ‎02-11-2013

I have tried this:

 

module tog ( input clock, output [1:0]out_wire );

 

(* RLOC = "X0Y0" *)reg outa;

(* RLOC = "X7Y7" *)reg outb;

 

assign out_wire = {outa,outb};

 

always@(posedge clock )

begin

outa <= !outb;

outb <= !outa;

end

 

endmodule

 

It works as long as you don't use arrays or generate loops. So  the array was modified to two single registers.

But thats an unacceptable restriction.

 

Then I tried the old Verilog Synthax, thought that could work with arrays:

 

module tog( input clock, output reg [1:0]out );

 

always@(posedge clock )

begin

out[0] <= !out[1];

out[1] <= !out[0];

end

 

// synthesis attribute RLOC of out_0 is X0Y0

// synthesis attribute RLOC of out_1 is X7Y7

endmodule

 

Result: the register reference is not found at synthesis. I tried any variation I can immagine. So probably it is not possible to reference an array within the module. But may be you have a better idea ?

 

 

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Scholar
Scholar
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Registered: ‎04-26-2012

@rschneid "Then I tried the old Verilog Synthax, thought that could work with arrays"

 

My rusty recollection of such old-style Verilog synthesis attributes (in Synplify) is that they need to be placed:

  - on the same line as the statement

  - ***BEFORE*** the trailing semicolon

 

EDIT : probably need to use the /* */ style comment as well

e.g.:

 

out[0] <= !out[1]   /* synthesis attribute RLOC of out_0 is X0Y0 */;


-Brian
 

 

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Visitor
Visitor
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Registered: ‎02-11-2013

Thanks Brian, but when written in a line, it should reference a to decalaration of an array, and not to an assignment.

I think it is not possible to constrain elements of an array.

 

Anyway, it would not help to fully constrain modules with any relevant functonality.

The HDL source code is not well suited to constrain elements, because elements like LUTs which are created in synthesis and mapping are not in the HDL code.

So my conclusion: the constraints can not be used to define macros in HDL code or in UCF files.

 

There was a way to create RPM macros via Floorplanner (XAPP422)  by exporting a constrained design to an NGC file.

This format, is also used by all the Xilinx IP cores.

But the feature was removed from Floorplanner.

 

 

To bring it to the point:

- Now there is no way to create RPM macros (beyond the complexity of a toggle flopflop) with all the Xilinx tools.

- Nobody a Xilinx seems to care about this.

I tink thats a desaster.

 

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Teacher
Teacher
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Registered: ‎03-31-2012

I tried to write a register bank generator in SystemVerilog where the RLOC is generated by ascii string manipulation but couldn't make it work because Vivado doesn't understand concatenation of string constants. And the case I opened was closed "never fix".

Of course you can do exactly this in VHDL with no problems. All string property management works in VHDL so you can generate attributes based on the generate index etc.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Scholar
Scholar
11,697 Views
Registered: ‎04-26-2012

@rschneid

"when written in a line, it should reference a to decalaration of an array, and not to an assignment"

 

Sorry, I was focused on 'old-style attribute not working', rather than what you were actually trying to accomplish :)

 

(The first time I hit that misplaced-semicolon issue, it took a considerable amount of head scratching to figure out what was wrong.)

 

"Now there is no way to create RPM macros (beyond the complexity of a toggle flopflop) with all the Xilinx tools."

 

I have done this in years past with VHDL; as mentioned by muzaffer, attribute strings are part of the language and can be computed in-line, or with a function, using the generate index. I don't know that you can do similar looped stuff in Verilog.

 

Some links:

 

1) recent forum thread with example:

http://forums.xilinx.com/t5/Synthesis/Implementing-loc-attribute-while-generating-components/m-p/480806/highlight/true#M11647

 

2)  old comp.arch.fpga thread where I posted a complete XC4000 carry chain example:

  https://groups.google.com/forum/#!msg/comp.arch.fpga/JuLB5sFE0lM/Wb4HyngcPxwJ

 

Associated code is now here:

   https://sites.google.com/site/fpgastuff/tc_test1.zip

 

 Note that this is very ancient, in particular:

   - XC4000 carry elements

   - old style RmCn location strings

   - homebrewed itoa instead of using integer'image

 

-Brian

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Visitor
Visitor
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Registered: ‎02-11-2013

Brian, thanks for the links, they may be useful for some future projects. But it is not possible in reasonable time to reduce a complex module to the level of LUTs, registers, carry chains... Thats exactly the task of Synthesis to Map tools. Then it is not possible to find a good placement without graphical support. I think a graphical tool like Floorplanner is needed to constrain the elements. All this was there some years ago and has been removed. So my questions to Xilinx are: why you do not support creation of RPMs any more ? Is there any intention to implemet this in future again? Are there any work arounds to create RPMs with graphical support by Floorplanner or FPGA Editor ?
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Visitor
Visitor
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Registered: ‎02-11-2013

@brimdavis do you have any examples for converting integers to strings in Verilog and how to concatenate them?
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Scholar
Scholar
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Registered: ‎04-26-2012

@rschneid "do you have any examples for converting integers to strings in Verilog and how to concatenate them?"

 

I don't know how to do this in Verilog ( most of my Verilog experience was pre-Verilog-2001 ).

 

Message #6 above from muzaffer indicated that he couldn't get it to work in SystemVerilog:

"

" I tried to write a register bank generator in SystemVerilog where the RLOC is generated

" by ascii string manipulation but couldn't make it work because Vivado doesn't understand

" concatenation of string constants. And the case I opened was closed "never fix".

"

 

Other discussions:

- see Allan Herriman's 10/8/2003 post on this comp.arch.fpga thread:

https://groups.google.com/forum/#!searchin/comp.arch.fpga/verilog$20rloc/comp.arch.fpga/eQncsQ2dCH8/sVNxUyE1wQ0J

 

- and this comp.lang.verilog thread about computing attribute strings:

https://groups.google.com/forum/#!msg/comp.lang.verilog/HjtSV8as_Hc/7Pjxcx_qSgcJ

 

-Brian

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