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Contributor
Contributor
515 Views
Registered: ‎01-10-2019

default block is never used

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Thank you read my question!

When I write my verilog code,I write a case ,but when I synth ,INFO tell me about this case is that default block is never used.

how to deal it?

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1 Solution

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Contributor
Contributor
407 Views
Registered: ‎10-25-2018

Re: default block is never used

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He's talking, I believe, about something like this:

module top (input logic a, output logic b);    
    always_comb begin
        case (a)
            1'b0: b = 1'b1;
            1'b1: b = 1'b0;
            default: b = 1'b1;
        endcase
    end
endmodule

which produes: INFO: [Synth 8-226] default block is never used.

@zengqh, you can remove the default case statement if it is not needed, or if it is needed, say in a "safe" state machine, then you can use the set_msg_config to suppress it.

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7 Replies
Moderator
Moderator
497 Views
Registered: ‎01-16-2013

Re: default block is never used

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@zengqh 

 

If you are using project mode then please share runme.log file present in <project>/<project>.runs/synth_1 folder else share vivado.log file which will have the complete message. 

 

--Syed

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Moderator
Moderator
442 Views
Registered: ‎03-16-2017

Re: default block is never used

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Hi @zengqh ,

It means you have not set the default option with case statement. Add it as shown below. Otherwise, your code will end up inferring latch. 

defautt.PNG

Regards,
hemangd

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Contributor
Contributor
421 Views
Registered: ‎01-10-2019

Re: default block is never used

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no ,I was set the default option. haha, it may means that this default is never used, do you think so ?
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Teacher drjohnsmith
Teacher
415 Views
Registered: ‎07-09-2009

Re: default block is never used

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suggestion

switch to systemverilog

ditch reg / wire an duse logic,

ditch always@ and use always_ff@ or always_comb@

ditch the (*) , give the compiler as much info as you can, and it will reward you 1000 times over.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
Contributor
Contributor
408 Views
Registered: ‎10-25-2018

Re: default block is never used

Jump to solution

He's talking, I believe, about something like this:

module top (input logic a, output logic b);    
    always_comb begin
        case (a)
            1'b0: b = 1'b1;
            1'b1: b = 1'b0;
            default: b = 1'b1;
        endcase
    end
endmodule

which produes: INFO: [Synth 8-226] default block is never used.

@zengqh, you can remove the default case statement if it is not needed, or if it is needed, say in a "safe" state machine, then you can use the set_msg_config to suppress it.

View solution in original post

Teacher drjohnsmith
Teacher
405 Views
Registered: ‎07-09-2009

Re: default block is never used

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If you want project to synth without any warnings, you could turn them all off...

careful with set_msg_config 

like all messages, they are there for a reason, and just cause this block it does no tmatter, other blocks it might, and set_msg_config  is global for project.

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
374 Views
Registered: ‎01-10-2019

Re: default block is never used

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yes, you are right. thank you!

thanks all for reply my questions!

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