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Explorer
Explorer
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Registered: ‎10-16-2018

define IN port as unsigned

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Hi ,

does it possible to define IN port as unsigned in VHDL, instesd of STD_LOGIC_VECTOR , as follow:

 

    gateway_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);

will be :

   gateway_in1 : IN unsigned(7 DOWNTO 0);

 

does that possible?

Thanks.

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Registered: ‎06-21-2017

The output of a FIR Compiler is a std_logic_vector.  VHDL is strongly typed.  You cannot compare a std_logic_vector to an unsigned.  The easiest thing to do is probably to make your thresold ports std_logic_vectors and do something like this in your code:

      if(unsigned(fir0) > thresh) then
         f_out <= "001" ;
      elsif (unsigned(fir1) > thresh) then
         f_out <= "010";

You need to typecast the std_logic_vector to unsigned so that you can compare values.

One more thing.  Are you sure you want to do an unsigned compare?  The FIR filter will output a two's compliment number.  A very small negative number will look like a huge positive number to unsigned.  0xFFFFFFFF is the smallest possible negative signed number, but the largest possible unsigned number.

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Teacher
Teacher
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Registered: ‎07-09-2009

in vhdl, a port is just that, a connection to the other entity.

provided the architecture that instantiates the entity and the entity have the same libraries , with the same types, you can connect them.

one thing,I doubt you are, but if your doing post synthesis simulation, then the only supported type at top level is std_logic and std_logic_vector, 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Registered: ‎01-22-2015

Yes, when you use the following library:

 use ieee.numeric_std.all;       

 

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Explorer
Explorer
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Registered: ‎10-16-2018

Hi @drjohnsmith , markg@prosensing.com 

I designed this threshold detector:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;  
use IEEE.math_real.all;


entity thresold is
    Port ( fir0 : in unsigned(31 downto 0);
           fir1 : in unsigned(31 downto 0);
           fir2 : in unsigned(31 downto 0);
           fir3 : in unsigned(31 downto 0);
           fir4 : in unsigned(31 downto 0);
           fir5 : in unsigned(31 downto 0);
           fir6 : in unsigned(31 downto 0);
           f_clk : in STD_LOGIC;
           f_out : out STD_LOGIC_VECTOR (2 downto 0));
end thresold;

architecture Behavioral of thresold is

constant thresh : integer := 3100000;

begin
     
  selector: process(f_clk)
  begin
    if(rising_edge(f_clk)) then
        
      if(fir0 > thresh) then
         f_out <= "001" ;
      elsif (fir1 > thresh) then
         f_out <= "010";
      elsif (fir2 > thresh) then      
          f_out <= "011";
      elsif (fir3 > thresh) then      
          f_out <= "100";  
      elsif (fir4 > thresh) then      
          f_out <= "101";
      elsif (fir5 > thresh) then      
         f_out <= "110";
       elsif (fir6 > thresh) then      
         f_out <= "111";                       
      end if;
      
    end if;
  end process selector; 
end Behavioral;

The Thrshold IP is capable of accept 7 FIR compilers (Filters) inputs. Then it is outputing only one signal depending on the threshold value.

But, When I run the simulation an error came up. The error is related to type matching, as shown below:

([VRFC 10-619] entity port fir0 does not match with type std_logic_vector of component port ["D:/Users/dell/Vivado_projects/FH_RX/FH_RX.ip_user_files/bd/RX/sim/RX.vhd":33])

I changed lines 33-39 from STD_LOGIC_VECTOR to unsigned , but the error is still exixsted pointing to the same lines !

Pls, how to solve this issue? I want my Threshold IP work.

Thanks.

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Registered: ‎06-21-2017

The output of a FIR Compiler is a std_logic_vector.  VHDL is strongly typed.  You cannot compare a std_logic_vector to an unsigned.  The easiest thing to do is probably to make your thresold ports std_logic_vectors and do something like this in your code:

      if(unsigned(fir0) > thresh) then
         f_out <= "001" ;
      elsif (unsigned(fir1) > thresh) then
         f_out <= "010";

You need to typecast the std_logic_vector to unsigned so that you can compare values.

One more thing.  Are you sure you want to do an unsigned compare?  The FIR filter will output a two's compliment number.  A very small negative number will look like a huge positive number to unsigned.  0xFFFFFFFF is the smallest possible negative signed number, but the largest possible unsigned number.

View solution in original post

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Teacher
Teacher
901 Views
Registered: ‎07-09-2009

Or,

 

as yo have deinfed threshold as integer, which has + and 0, where as your comparing it to unsinged,

  why not define threshold as unsigned,

   

as said above, stongly typed, you cant just do a C thing and let the tools guess.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar
Scholar
879 Views
Registered: ‎08-01-2012

@ahmed_alfadhel 

This doesnt appear to be an error in the code you posted, but an error where you are trying to instantiate the threshold entity.

I suspect that while you have updated the entity, you have a component declaration elsewhere that uses std_logic_vector for fir0,1... etc instead of unsigned. This will cause the type missmatch error you have.

The easiest fix here is to never use components when instantiating a VHDL entity, and use direct instantiation that made an appearance with VHDL 1993 (maybe your examples or textbook are from before then? - many older texts, and even newer examples, dont seem to know about this 26 year old feature)

thresh_inst : entity some_lib.threshold
port map (
-- etc etc

This way, you'll get a syntax error when you compile it (ie, within second) and you'll get a wobbly red line under the offending port, rather than a a more cryptic error when you try and elaborate the design for simulation (which may take much longer).

Remember, components are just a copy/paste of your entity, and tell the compiler to use the component and you'll map the entity later - its very prone to copy paste error as you need to keep 2 copies of the same code.

Stop using components!

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Explorer
Explorer
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Registered: ‎10-16-2018

One more thing.  Are you sure you want to do an unsigned compare?  The FIR filter will output a two's compliment number.  A very small negative number will look like a huge positive number to unsigned.  0xFFFFFFFF is the smallest possible negative signed number, but the largest possible unsigned number.


Hi @bruce_karaffa ,

Thank you for instructing me to use typecast (signed).

 selector: process(f_clk)
  begin
    if(rising_edge(f_clk)) then
        
      if(signed(fir0) > thresh) then
         f_out <= "001" ;
      elsif (signed(fir1) > thresh) then
         f_out <= "010";
      elsif (signed(fir2) > thresh) then      
          f_out <= "011";
      elsif (signed(fir3) > thresh) then      
          f_out <= "100";  
      elsif (signed(fir4) > thresh) then      
          f_out <= "101";
      elsif (signed(fir5) > thresh) then      
         f_out <= "110";
      elsif (signed(fir6) > thresh) then      
         f_out <= "111";                       
      end if;
      
    end if;
  end process selector; 

Thank you all guys for your notes.

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Scholar
Scholar
836 Views
Registered: ‎08-01-2012

@ahmed_alfadhel 

 

This isnt very clear what you've done to solve this? are FIR0/1 etc still unsigned, or are they std_logic_vector? casting an unsigned to signed is really something you should NOT be doing. If that is that is the case, all types should have been signed in the first place.

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Explorer
Explorer
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Registered: ‎10-16-2018

Hi @richardhead ,

Kindly,

I edited my IP core (Threshold) to make all fir# inputs to be defined as STD_LOGIC_VECTOR , as follow:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;  
use IEEE.math_real.all;


entity thresold is
    Port ( fir0 : in STD_LOGIC_VECTOR(31 downto 0);
           fir1 : in STD_LOGIC_VECTOR(31 downto 0);
           fir2 : in STD_LOGIC_VECTOR(31 downto 0);
           fir3 : in STD_LOGIC_VECTOR(31 downto 0);
           fir4 : in STD_LOGIC_VECTOR(31 downto 0);
           fir5 : in STD_LOGIC_VECTOR(31 downto 0);
           fir6 : in STD_LOGIC_VECTOR(31 downto 0);
           f_clk : in STD_LOGIC;
           f_out : out STD_LOGIC_VECTOR (2 downto 0));
end thresold;

architecture Behavioral of thresold is


constant thresh : integer := 3100000;

begin
    
  selector: process(f_clk)
  begin
    if(rising_edge(f_clk)) then
        
      if(signed(fir0) > thresh) then
         f_out <= "001" ;
      elsif (signed(fir1) > thresh) then
         f_out <= "010";
      elsif (signed(fir2) > thresh) then      
          f_out <= "011";
      elsif (signed(fir3) > thresh) then      
          f_out <= "100";  
      elsif (signed(fir4) > thresh) then      
          f_out <= "101";
      elsif (signed(fir5) > thresh) then      
         f_out <= "110";
      elsif (signed(fir6) > thresh) then      
         f_out <= "111";                       
      end if;
      
    end if;
  end process selector; 
end Behavioral;

What is problem in my VHDL code? 

Thanks

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Scholar
Scholar
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Registered: ‎08-01-2012

@ahmed_alfadhel 

Then there is no problem. I was worried the ports were still unsigned.

I still think your ports should be signed type rather than slv.

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Registered: ‎10-16-2018

@richardhead 


@richardhead wrote:

I still think your ports should be signed type rather than slv.


 This will lead to type mismatch with incomming connections from FIR IP cores. I tested this case with unsighed type.

@drjohnsmith also said that in the first reply.

Thanks,

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Scholar
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Registered: ‎08-01-2012

@ahmed_alfadhel 

You havent shown the code where you instantiate the core. Anything is possible, and like I said I suspect your component declaration is incorrect (when you use signed type).

You can always do type conversion in the top level file (even in the port map)

inst : entity lib.some_ent:
port map (
  signed_ip <= signed(some_slv_signal),
  -- etc
);
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Registered: ‎06-21-2017

I think that @richardhead is pointing out is that while your filter may have SLV ports, it is treating the data as signed.  You have coefficients greater than zero and less than zero.  They are signed.  You are inputting sine waves centered around zero.  The output of the filter will have values less than zero as well as greater than zero.  The filter's output should be treated as signed.  Remember, an SLV of 0xFFFFFFFF means -1 if typecast as signed, it means 4,294,967,295 if typecast as unsigned.  If you want to compare the magnitude of your filters' outputs to an unsigned threshold, you need to convert any negative numbers to positive numbers first.

Additionally, you should think about this.  Even the filter with the output of the greatest magnitude will cross zero periodically.  One of the other filters' outputs will probably have a greater magnitude at that time.  Your selection will most likely chatter a bit.

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Registered: ‎10-16-2018

Hi @bruce_karaffa ,


@bruce_karaffa wrote:

 If you want to compare the magnitude of your filters' outputs to an unsigned threshold, you need to convert any negative numbers to positive numbers first.

 


How to do that (you need to convert any negative numbers to positive numbers first) ?

Thanks.

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Registered: ‎06-21-2017

Write more code.  Assuming a signed type input and an unsigned outputyou could have something like:

Rectifier : process(clk)
begin
   if rising_edge(clk) then
      if (ProcessInput = x"80000000") then
         ProcessOutput <= unsigned(x"7fffffff");
     elsif (ProcessInput < 0) then
        ProcessOutput <= unsigned(x"00000000" - ProcessInput);
     else
        ProcessOutput <= unsigned(ProcessInput);
     end if;
   end if;
end process;

I think you have a 26 bit filter output sign extended to 32 bits, so you may not need to deal with the special case of x"80000000" but in general, it's best not to forget this case.  Also the minus sign "-" can be a unary operator in addition to a subtraction operator, so you probably don't need the x"00000000 - ProcessInput, and can probably just use           (- ProcessInput).  Give it a try.  There are other coding styles for this operation too. 

Note that this will rectify your signal.  This means all of your negative values become positive.  This introduces lots of harmonics in your signal.  You can do this for the input to the threshold function to choose which frequency you want to process, but you will probably want to do your processing on the unrectified signal.