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defining a input signal as a clock signal

Scholar
Posts: 914
Registered: ‎04-07-2008

defining a input signal as a clock signal

I have a signal that is created from the XORing of two signals,  Data Strobe decoding for the clock.  Then I take that signal

and run it into a BUFG.   This signal is fed into a Hierachical Block where the input name of the block is different than

the clock signal coming out of the BUFG. 

 

I am looking in the Constraints editor for the signal name so I can constain the clock period of the derived clock signal but I can not find it in the list of clocks in the constraint editor.   

 

Is there a attribute I can put in VHDL modules that will define the derived signal as a clock.

 

Thank You

 

Moderator
Posts: 8,791
Registered: ‎02-27-2008

Re: defining a input signal as a clock signal

g,

 

If the signal drives the clock pins of DFF in IOB or CLB, then it is a clock (it is implicit in what it gets wired to).

 

I would look in FPGA_Editor, and find the name of the clock net, as you will need a PERIOD constraint on this clock to allow the tools to know what to do about the timing.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Moderator
Posts: 8,791
Registered: ‎02-27-2008

Re: defining a input signal as a clock signal

g,

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf

 

page 35, 47 ...

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Scholar
Posts: 914
Registered: ‎04-07-2008

Re: defining a input signal as a clock signal

[ Edited ]

Thank You Austin,

  I looked at the RTL Schematic and I can see the name of the signal there.  I will try to constrain the signal (clk)

and see if it works.  The title of the message should have said defining a internal signal as a clock signal.

Thank You,

  Gary

 

Scholar
Posts: 914
Registered: ‎04-07-2008

Re: defining a input signal as a clock signal

 

 

I tried using my net name in my case, GLOBAL_CAM_DS_CLK.

 

It could not find the signal eventhough I saw this name in the FPGA Editor.

 

So I tried using the Timing Analyzer and created a Report on Clock Regions  in the report it showed the following

 

 

 

 CAM_IF_TP/CAM_INPUT_PATH1/CAM_ACCPT/mux_cam_clkf

     CAM_IF_TP/CAM_INPUT_PATH1/GLOBAL_CAM_DS_CLK  
 
 
 

 

Now I tried to use these statements:

 

NET "CAM_IF_TP/CAM_INPUT_PATH1/GLOBAL_CAM_DS_CLK" TNM_NET = CAM_IF_TP/CAM_INPUT_PATH1/GLOBAL_CAM_DS_CLK;
TIMESPEC TS_GLOBAL_CAM_DS_CLK = PERIOD "GLOBAL_CAM_DS_CLK" 20 ns HIGH 50%;  

 

 

To me it looks like internally generated clocks use a more complicated name.  If I used just the 

name GLOBAL_CAM_DS_CLK it will not find the Net.

 

It is now appearing on the synthesis report as CAM_IF_TP/CAM_INPUT_PATH1/GLOBAL_CAM_DS_CLK

 

Thanks Again