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Scholar
Scholar
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Registered: ‎08-14-2007

difference between synthesis and map process

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Hi,

 

I am a little confused about what synthesis do and what map process (inside implementation) do

 

I found these definitions in a xilinx website

 

"sytnesis process converts HDL (VHDL/Verilog) code into a gate-level netlist (represented in the terms of the UNISIM component library, a Xilinx library containing basic primitives)."

 

"Mapping. During the map phase the SIMPRIM primitives from an NGD netlist are mapped on specific device resources: LUTs, flip-flops, BRAMs and other"

 

So i have two questions:

 

1. What kind of primitives are in the UNISIM library?? this primitives are "general digital resources" like FFs, Muxs, gates, etc?? or these primitives actually contains FPGA resources like LUTs, Slices and BRAMs??

 

2. I understand that UNTIL the mapping process is when actual design is translate into FPGA specific resources (LUT, Slices, etc), right?? , BUT why when i see synthesis report (without doing mapping), this report already contains FPGA resources??, is it not suppose that FPGA resources comes until mapping??

 

I already understand Translate, Place and Route process but i am not sure about the difference between synthesis and map

Thanks for your answers :)

 

 

 

 

 

 

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Scholar
Scholar
17,590 Views
Registered: ‎02-27-2008

p,

 

Yes.

 

 

There a lot of details, but I believe this is a good simplification of what is going on.

 

Synthesis is targeted at some physical library of existing functions for a device.  If I take my veriog, I can ask my synthesis tool to synthesize it for my ASIC standard library, or for my Spartan 6 (no the syntheiss tool supplied by Xilinx, but say some more generic tool that is able to use anyone's library).

 

Then, in place and route, the tools (Xilinx) takes the synthesizxed design, maps the elements to appropriate spots based on devilishly clever algorithms, in order to best meet the constraints (timing, IO pin location).  Then route starts, trying to wire things up with interconnect resources (again applying the constraints all the while).  If a route can't be done per the constraints, there follows a rip up, re-map, and re-route phase for that element's path.  At some point, the tool is done (it doesn't find the best result, just a result which meets the constraints).  If it can't meet the constraints after some pre-determed number of attempts, it gives up, and results in warnings and errors (warning: I didn't meet the constraints, and error: you have unrouted nets).

 

At that point, you can try a different strategy, or change the constraints, or take the design as far as it got, and try to finish it by hand in FPGAEditor (only really useful if there are one, or a few of paths left to do).

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

1.  The primitives are the DFF, LUT, etc. (all specific to the FPGA device family)

 

2.  See above (1.).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Registered: ‎08-14-2007

Hi,

 

So lets see if i understood,

 

So Synthesis calculates resources in terms of FFs, LUTs, Slices, etc but for a FPGA family (Virtex-4, Spartan-3 ,etc). And then  mapping converts this resources in terms again of FFs, LUTs, Slices, etc, but for specific FPGA device??, is it correct?

 

So in theory if i synthesize the same design for a specific family, lets say Virtex-5 but i change the device to LX110, FX130T, SX50, etc, it will give me the same resources??

 

thanks again

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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

Yes.

 

 

There a lot of details, but I believe this is a good simplification of what is going on.

 

Synthesis is targeted at some physical library of existing functions for a device.  If I take my veriog, I can ask my synthesis tool to synthesize it for my ASIC standard library, or for my Spartan 6 (no the syntheiss tool supplied by Xilinx, but say some more generic tool that is able to use anyone's library).

 

Then, in place and route, the tools (Xilinx) takes the synthesizxed design, maps the elements to appropriate spots based on devilishly clever algorithms, in order to best meet the constraints (timing, IO pin location).  Then route starts, trying to wire things up with interconnect resources (again applying the constraints all the while).  If a route can't be done per the constraints, there follows a rip up, re-map, and re-route phase for that element's path.  At some point, the tool is done (it doesn't find the best result, just a result which meets the constraints).  If it can't meet the constraints after some pre-determed number of attempts, it gives up, and results in warnings and errors (warning: I didn't meet the constraints, and error: you have unrouted nets).

 

At that point, you can try a different strategy, or change the constraints, or take the design as far as it got, and try to finish it by hand in FPGAEditor (only really useful if there are one, or a few of paths left to do).

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
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Registered: ‎08-14-2007

Ok i am agreed with you,

 

BUT i think place and route comes after mapping process, so in fact, there are 3 steps after synthesis that are: Map, Place and Routing. I understand that Place puts resources in specific spots of the device and Routing make all the interconections but i was not sure about Map, because in the past i confused Map and Place, and i think they are different things.

 

Thanks :)

 

 

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Han you help me please. I want
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@etti411g wrote:
Han you help me please. I want

"Help me, Obi Wan Kenobi, you're my only hope.'

 

BTW: Han shot first.

----------------------------Yes, I do this for a living.
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bassman59 wrote:

etti411g wrote:
Han you help me please. I want

"Help me, Obi Wan Kenobi, you're my only hope.'

 

BTW: Han shot first.


Yes, but Obi-Wan built the Bridge Over the River Kwai.  Before he blew it up.

 

This is the help you are looking for.

 

-- Bob Elkind

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Historian
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@eteam00 wrote:

@bassman59 wrote:

@etti411g wrote:
Han you help me please. I want

"Help me, Obi Wan Kenobi, you're my only hope.'

 

BTW: Han shot first.


Yes, but Obi-Wan built the Bridge Over the River Kwai.  Before he blew it up.

 

This is the help you are looking for.

 

-- Bob Elkind


Ah, yes, Sir Alec Guinness was most excellent in that. He was also the butler in the film version of Neil Simon's "Murder By Death." 

----------------------------Yes, I do this for a living.
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