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Visitor
Visitor
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Registered: ‎07-24-2013

different synthesis strategies without IP's

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I need different synthesis strategies for my design on an XC7S6. I have to translate 2 components by “Default” to place them exactly for a critical timing. The rest has to be translated with "AreaOptimized_high" so that everything fits into the chip. What is the best way to do this? I tried to use the components as IP, but the placement is not done according to my constraint.

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: different synthesis strategies without IP's

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Hi @mauell ,

As per your requirment you can try BLOCK_SYNTH property.

For more information on that, check the below UG:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

Thanks,

Raj

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Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎05-22-2018

Re: different synthesis strategies without IP's

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Hi @mauell ,

As per your requirment you can try BLOCK_SYNTH property.

For more information on that, check the below UG:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

Thanks,

Raj

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Visitor
Visitor
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Registered: ‎07-24-2013

Re: different synthesis strategies without IP's

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Thank you so much, that's how it worked!
Previously I had only tried to put the "BLOCK_SYNTH" property in the vhdl source, which was ignored.

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