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4,229 Views
Registered: ‎01-22-2015

disable source file

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ug893 says, “You can toggle source files between enabled and disabled to define different design configurations”.  

 

In Vivado, this is done using commands like the following:

              

                 set_property is_enabled false [get_files <file_name>]

 

Can someone describe an example of using enable/disable for a source file?

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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

Suppose you have a design that one of its components is an FIR filter named: my_fir.

You have 5 variations of this component - all with the same ports but different internal architecture.

 

By kipping different variations of my_fir in 5 separate files you'll be able to choose which one to use (via diabling/enabling) without any changes in your HDL. 

 

It wouldn't be my methodology of doing things - but it's one use I can think of.

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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

 

When you want a file not to participate in the synthesis process for example...

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4,170 Views
Registered: ‎01-22-2015

@shaikon

 

Simply disabling a file that describes a component causes problems if the component is instantiated in your project and connected to other components(files) that are enabled.  Synthesis tolerates the disabled file/component and shows it as a black box.  However, implementation throws errors and is unable to complete.  I cannot see how this is useful.

 

Perhaps a project could have different top-level components/files and you could enable only one top-level component.  This could be useful.

 

Any other examples or reasons for using file enable/disable?

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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

You're correct - but I never said that the file in question is part of the hierarchical tree...

 

One scenario I can think of is enabling and disabling a file (or many files) to create different design configuration with zero change in HDL.

 

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4,154 Views
Registered: ‎01-22-2015

 

     ...create different design configuration with zero change in HDL.

Can you describe an example of this?

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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

Suppose you have a design that one of its components is an FIR filter named: my_fir.

You have 5 variations of this component - all with the same ports but different internal architecture.

 

By kipping different variations of my_fir in 5 separate files you'll be able to choose which one to use (via diabling/enabling) without any changes in your HDL. 

 

It wouldn't be my methodology of doing things - but it's one use I can think of.

View solution in original post

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4,123 Views
Registered: ‎01-22-2015

Thanks for example and for continuing this discussion.

 

I am not familiar with “kipping”.  However, I understand your example of 5 separate files for component, my_fir – all with same ports but different internal architecture.  Also, for this to work, I think it is required that all 5 components be named, my_fir.  Is it possible for name of a file (that describes a component) to be different from the name of the component?

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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

Sorry, I meant "keeping" of-course.

 

"Also, for this to work, I think it is required that all 5 components be named, my_fir"

That's true

 

"Is it possible for name of a file (that describes a component) to be different from the name of the component?"

Yes.

 

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4,094 Views
Registered: ‎01-22-2015

-again thanks!

 

I am using Vivado v2017.3 and VHDL.  For my own custom component, I can use multiple files (each having a different name) to describe variations of the same component.   -very cool !

 

However, for IP components, the file name and the component name seem tightly linked.  Do you know how to change the file name but not the component name for Xilinx/Vivado IP?

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shaikon
Voyager
Voyager
4,081 Views
Registered: ‎04-12-2012

I am using Vivado v2017.3 and VHDL.  For my own custom component, I can use multiple files (each having a different name) to describe variations of the same component.   -very cool !

If were're talking about small variations in functionality - I prefer compile time configuration via HDL generics (instead of keeping duplicates). But it's a matter of flavor.   

 

However, for IP components, the file name and the component name seem tightly linked.  Do you know how to change the file name but not the component name for Xilinx/Vivado IP?

No, sorry. 

But why not group all components with the same functionality under one hierarchy and instantiate the one you want to use ?

 

 

3,289 Views
Registered: ‎01-22-2015

@shaikon

 

Thanks for many replies and much help!

 

I agree that enabling/disabling files is not the best way to explore different configurations - but I had fun learning about it with your help.

 

Cheers,

Mark

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nasajohnc
Observer
Observer
3,210 Views
Registered: ‎03-22-2018

 My two cents. Haven't you guys heard of "versions" and version control? OF COURSE you can have multiple versions of a file with same name. In a large organization it would create mass confusion to have to rename all your files for each version.

Anyway, I myself have seen this problem in Vivado where it confuses files from different locations, but the same name. I have specifically told Vivado where to find a file, yet it will STILL confuse that file with another of the same name. Vivado needs to be much smarter in how it organizes files.

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3,199 Views
Registered: ‎01-22-2015

Hi John  - thanks for two cents.

I hear what you're saying and I'm sure Vivado could (with tweaking) do this type of file management.  Usually, we just need some way to distinguish between a few different versions of a component.  Using different file names does the job, whereas using different file names and possibly different directory names seems like extra and unnecessary bookkeeping.  -personal preferences, I guess.

-have a good day!

Mark

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