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bbinb
Adventurer
Adventurer
250 Views
Registered: ‎07-09-2014

does ram_style attribute has no effect in Vivado 2020.1

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Hi,

I try to infer block RAM by using Xilinx VHDL language templates. I use ram_style attribute as follows:

...

type t_my_ram is array (0 to 134) of std_logic_vector (7 downto 0);

signal my_ram : t_my_ram := ( 0 => x"AA", 1 => x"BB", 5 => x"CC", 9 => x"DD", others => (others => '0'));

attribute ram_style : string;

attribute ram_style of my_ram : signal is "block";

...

begin

process (clk) begin

if (rising_edge(clk)) then

   if (ram_we = '1') then

      my_ram(ram_addr) <= ram_di;

   end if;

end if;

end process;

ram_do <= my_ram(ram_addr);

...

But after I synthesized the RTL, I get LUT utilization used as memory, instead of Block RAM in the synthesis report.

After all, I dont want Vivado to choose RAM type, why ram_style attribute does not work? Do I miss sth?

Thanks,

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bbinb
Adventurer
Adventurer
243 Views
Registered: ‎07-09-2014

!!! Beginner mistake !!!

I had just re-used another file content and the process block which infers directly distributed RAM as the RAM output assignment is not in a clocked process, which causes the distributed RAM content.

sorry the RAM output assignment should be in a clocked process content as:

  

process (clk) begin

if (rising_edge(clk)) then

   if (ram_we = '1') then

      my_ram(ram_addr) <= ram_di;

   end if;

ram_do <= my_ram(ram_addr);

end if;

end process;

 

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richardhead
Scholar
Scholar
243 Views
Registered: ‎08-01-2012

You don't show the whole code,  but the reason is likely because the address is not registered.  Only lutram can do asynchronous read.

bbinb
Adventurer
Adventurer
244 Views
Registered: ‎07-09-2014

!!! Beginner mistake !!!

I had just re-used another file content and the process block which infers directly distributed RAM as the RAM output assignment is not in a clocked process, which causes the distributed RAM content.

sorry the RAM output assignment should be in a clocked process content as:

  

process (clk) begin

if (rising_edge(clk)) then

   if (ram_we = '1') then

      my_ram(ram_addr) <= ram_di;

   end if;

ram_do <= my_ram(ram_addr);

end if;

end process;

 

View solution in original post

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bbinb
Adventurer
Adventurer
241 Views
Registered: ‎07-09-2014

I think my problem is about this RAM issues, like for most people usually the same case as I search through the web: "NOT USING LANGUAGE TEMPLATE OF XILINX PROPERLY".

Just now I saw a post of  "anusheel" in another thread:

To infer a BRAM, logic should have:

  1. Registered outputs
  2. All Output Registers have the same control signals.
  3. Design should have synchronous reset

Thanks,
Anusheel

So my problem was also not using registered output.

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