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babai_14
Visitor
Visitor
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Registered: ‎09-24-2020

error in jk master slave flipflop

module msjk_ff(
input j,
input k,
input clk,
output q,
output qbar
);
assign iclk=~clk;

wire Mq; // The master's q output.
wire Mqbar; // The master's qbar output.
masterslave_jkff master(Mq,Mqbar,clk,j,k,q,qbar);
masterslave_jkff slave(q,qbar,iclk,Mq,Mqbar);
endmodule

module masterslave_jkff(
input j,
input k,
input clk,
output q,
output qbar
);

wire nand1_out; // output from nand1
wire nand2_out; // output from nand2

assign q=1'b1;
assign qbar=1'b0;

nand(nand1_out, j,clk,qbar);
nand(nand2_out, k,clk,q);
nand(q,qbar,nand1_out);
nand(qbar,q,nand2_out);
endmodule

the output coming as-

Screenshot (24).png

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1 Reply
markcurry
Scholar
Scholar
381 Views
Registered: ‎09-16-2009

The primitive "nand" defaults to 0-delay.  Dig into the language and figure out how to model some delay through those cells.  Hint - don't model the delays to be exactly the same through all the nand gates.

Also, you're going to have to figure out how to bias your initial conditions such that the startup state isn't undefined (I.e what values q, and qbar take at time zero).

Be aware, this learning experience you're going through is a valuable lesson.  However, it's not the way one designs with FPGAs.  But as a learning tool, you'll be ok.

Edit to add : You've posted this question in the "Synthesis" forum - however none of what you're doing is really synthesizable.  Your experiments should only be done in simulation.

Regards,

Mark

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