The primitive "nand" defaults to 0-delay. Dig into the language and figure out how to model some delay through those cells. Hint - don't model the delays to be exactly the same through all the nand gates.
Also, you're going to have to figure out how to bias your initial conditions such that the startup state isn't undefined (I.e what values q, and qbar take at time zero).
Be aware, this learning experience you're going through is a valuable lesson. However, it's not the way one designs with FPGAs. But as a learning tool, you'll be ok.
Edit to add : You've posted this question in the "Synthesis" forum - however none of what you're doing is really synthesizable. Your experiments should only be done in simulation.