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Advisor ronnywebers
Advisor
2,192 Views
Registered: ‎10-10-2014

error in synthesised schematic of inferred SRL16E ?

I used the shift register example code from UG901

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;

entity singlebit_delay is
generic (
    DEPTH       : integer := 10
);
port (
    reset                       : in std_logic;
    clock                       : in std_logic;
       
    din                         : in  std_logic;
    dout                        : out std_logic
);
end singlebit_delay;

architecture Behavioral of singlebit_delay is

	signal shift_reg : std_logic_vector(DEPTH-1 downto 0);

begin

	process(clock)
	begin
		if rising_edge(clock) then
			shift_reg <= shift_reg(DEPTH-2 downto 0) & din;
		end if;
	end process;

    dout <= shift_reg(DEPTH-1);

end Behavioral;

instantiation is as follows :

 

    singlebit_delay_i : singlebit_delay
    generic map( DEPTH => 9 )
    port map( reset => reset, clock => clock, din => s_ms_frame_detect, dout => ms_frame_complete);

now simulation after synthesis is ok, but I'm puzzled by the synthesised schematic :

 

9-bit SR.png

 

according to UG953, depth of the SRL16E primitive is : 

 

(8 x A3) + (4 x A2) + (2 x A1) + A0 + 1

(8 x   0) + (4 x    0) + (2 x   1) +  0  +  1 =  3

 

adding to that the extra FF that seems to be inferred all times as the final bit of a shift register, I see only 4 flip-flops of delay?

 

note that post-synthesis simulation shows 9 clock cycles delay, which is expected. Is this a bug in the schematic representation of the SRL16E primitive?

 

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Advisor ronnywebers
Advisor
2,187 Views
Registered: ‎10-10-2014

Re: error in synthesised schematic of inferred SRL16E ?

I also want to note some strange inference results, I tried out to change the generic 'DEPTH' parameter from 2 to 8, and checked each time the synthesised schematic. That gave me the following results :

 

DEPTH = 2 (does not infer SRL16E)

 

2-bit sr.png

 

DEPTH = 3 (from here on infers SRL16E)

 

3-bit sr.png

 

DEPTH = 4

 

4-bit SR.png

 

DEPTH = 5

 

5-bit SR.png

 

DEPTH = 6

 

6-bit SR.png

 

DEPTH = 7

 

7-bit SR.png

 

DEPTH = 8

 

8-bit SR.png

 

DEPTH = 9

 

9-bit SR.png

 

So a few things that I noticed :

 

1) from DEPTH >= 3, an SRL16E is inferred, which sounds logical to me

2) after the SRL16E, there is always at least 1 FF : Question : is this to improve timing?

3) for DEPTH = 6, and DEPTH = 7, additional FF's are inferred, instead of putting the delay steps into the SRL16E -> why is this?

4) for DEPTH = 8 and DEPTH = 9, the A values look incorrect, and that keeps on going for larger values of DEPTH, see my original question, this looks like an error to me (?)

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