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Newbie fabioacosta
Registered: ‎11-02-2014

externally triggered time counter in verilog

Hi I'm new to the fpga world, just got a Xilinx Spartan 3E and started playing around with it in verilog with the ISE design tools.

My frustration came when I try to use 2 external triggers to activate counters. My goal is to make a program that when given 3 posedges of a push button in a range of 5 seconds turns on a led. If the 5 seconds go and there haven't been 3 events from the push, resets and restart the process.

I tried to code this and the concept was something like this

Always@(posedge push)
**if first push then flag=1**

Always @(posedge clock)
** if flag==1 then start counter
       **check function for pushes and time reset

This had the issue that I had to change registers on both blocks so I've been told to put both processes in one block. The problem with it is that I don't see a way to make the push posedge work since the clock is always faster.

Is there a way for me to activate a clock counter after another posedge event and make it synthesizable. I know for a fact this is a possible implementation  using a counter that controls another one via reset or enable and I would just make it through schematic if it wasn't for the absurdly large counter that is needed with a 50Mhz clock.

Please help me with this and I'll be eternally grateful.

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2 Replies
Mentor hgleamon1
Registered: ‎11-14-2011

Re: externally triggered time counter in verilog

You should always synchronise external signals to your internal clock. This helps to avoid metastability problems and also ensures that all associated logic will be clocked from one source, helping with synchronisation issues and timing.


Push buttons are usually pretty "noisy" - the contacts bounce quite a lit before making a reliable connection that is usable in the higher speed digital domain, so after synchronising the push button input, you'll probably want to debounce it (e.g. a low pass filter).


Then, after detecting the first valid push, you want to start your counter. At 50 Mhz, 5 seconds equates to 250 million clock cycles, which may be represented in binary in 28 bits. Depending on the size of your S3E, I would have thought that you'll have abundant resources to implement a 28 bit counter (it is not absurd to have a counter of this size).


You also want to keep check on whether or not the push button has been pressed the required number of times before the counter wraps around - I suggest a 3 bit shift register to shift in the filtered push button input. When the shift register is 3b'111 and the counter is less than 250 million, then the LED turns on.


In terms of digital design, what you require is pretty basic HDL (I'm more of a VHDL person). You just need to break your design down into functional blocks (all sensitive to the FPGA clock).


Hope this helps.

"That which we must learn to do, we learn by doing." - Aristotle
Mentor hgleamon1
Registered: ‎11-14-2011

Re: externally triggered time counter in verilog

There's a very thorough discussion on debouncing switches to be found here

"That which we must learn to do, we learn by doing." - Aristotle
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