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Observer ardupas
Observer
7,207 Views
Registered: ‎10-03-2013

extra added BUFG in netlist, why?

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Hello guys,

I've inserted an netlist in Vivado 2014.4 project which had no bufg.

During implementation of the the top, I've got an error because 3 extra bufg have been added inside the netlist module on clock signals, and it's redondant with other bufg in the design.

How can we avoid that vivado add extra bufg in inserted netlist ?

I tried with the black_box attribute but it's not working.

 

Thank you for your help.

Arnaud.

 

 

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Xilinx Employee
Xilinx Employee
13,943 Views
Registered: ‎09-20-2012

Re: extra added BUFG in netlist, why?

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Hi @ardupas

 

What is the implementation error you are facing?

 

Are you using Vivado synthesis? 

 

You can use clock_buffer_type attribute to prevent insertion of BUFG. Refer to page-155 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug912-vivado-properties.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
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3 Replies
Xilinx Employee
Xilinx Employee
13,944 Views
Registered: ‎09-20-2012

Re: extra added BUFG in netlist, why?

Jump to solution

Hi @ardupas

 

What is the implementation error you are facing?

 

Are you using Vivado synthesis? 

 

You can use clock_buffer_type attribute to prevent insertion of BUFG. Refer to page-155 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug912-vivado-properties.pdf

 

Thanks,

Deepika.

Thanks,
Deepika.
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Moderator
Moderator
7,199 Views
Registered: ‎07-21-2014

Re: extra added BUFG in netlist, why?

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@ardupas

 

Can you try using post-synthesis project flow to add netlist in the design to see the number of BUFGs and launch implementation to see whether tool is able to pass.

 

Thanks,
Anusheel
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Observer ardupas
Observer
7,170 Views
Registered: ‎10-03-2013

Re: extra added BUFG in netlist, why?

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I had the error ' nb of BUFG is limited to 16 in bottom half SRL0', after synthesis and implementation in vivado project mode.

I can not use post synthesis flow, because I have a mix of vhdl new sources and inserted netlist.

 

Now it is resolved with the attribute clock_buffer_type set on "NONE" on clocks nets.

 

Thank you very much for your help.

Arnaud.

 

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