I'm trying to compile the VHDL code below. I set Vivado to use VHDL 2008. The synthesis failed in some cases but I definetely do not see the reason.
entity pouet is
-- Main signals
CLK : in std_logic;
RESETN : in std_logic;
-- Data out
dout : out std_logic_vector(7 downto 0)
architecture Behavioral of pouet is
constant coeff_8b : ufixed(4 downto -3) := "10101010";
-- OPTION A1
constant coeff : ufixed(7 downto -6) := to_ufixed (0.29, 7, -6);
-- OPTION A2
--constant coeff : ufixed(7 downto -6) := "00000000010011";
if (rising_edge (CLK)) then
if(RESETN = '0') then -- synchronous reset
dout <= (others => '0');
-- OPTION B1
dout <= to_slv(resize(coeff,7,0));
-- OPTION B2
--dout <= to_slv(coeff_8b);
When I try to synthesize with option A1, I get the following error:
[Synth 8-421] mismatched array sizes in rhs and lhs of assignment
Everything runs smoothly with option A2... but I do not understand why the first option does not work.
If I now try to synthesize with option A2 (which works) and option B1, I get the error:
[Synth 8-690] width mismatch in assignment; target has 8 bits, source has 31 bits
Where does the "31 bits" come from?
If i synthesize with option B2 only, it seems to work.