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Anonymous
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float_pkg and float IP core

Hi,

      I am using float_pkg from www.eda.org/fphdl. I wrote a VHDL code using this package to evaluate the following expression just as a beginning step. c=(a*b+a+2)*a where 'a','b' and 'c' are IEEE 754 32 bit floating point data.

 

Here is the VHDL code using package:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.float_pkg.ALL;

entity understand_1 is
       port(a,b: in float32;
	       clk: in std_logic;
		  c: out float32
             );
end entity;

architecture arch of understand_1 is
begin
     process(clk)
	    variable answer1,answer2,answer3:float32;
		 begin
		
		      if(rising_edge(clk)) then
					  
		             answer1:=a*b;
			      answer2:=a+to_float(2);
			      answer3:=answer1+answer2;
			      c<=answer3*a;
						  
		      end if;
    end process;
end architecture;

 

After that I wished to use float IP core instead of the package. I used floating-point 5.0 present in Xilinx ISE Project navigator 14.7. Since IP cores can be used only using component creation(entity modules), I re-structured the above program in the following way. Here add_ip and mul_ip are floting point IP's generated.

 

VHDL code using IP core

library IEEE;
use IEEE.std_logic_1164.ALL;


entity float_ip is
       port( a,b:in std_logic_vector(31 downto 0);
             clk:in std_logic;
               c:out std_logic_vector(31 downto 0)
           );
end entity;

architecture arch of float_ip is

component add_ip
          port(   a,b:in std_logic_vector(31 downto 0);
                  clk:in std_logic;
               result:out std_logic_vector(31 downto 0)
              );
end component;
      
component mul_ip
          port(   a,b:in std_logic_vector(31 downto 0);
                     clk:in std_logic;
                 result:out std_logic_vector(31 downto 0)
              );
end component;


signal answer1,answer2,answer3:std_logic_vector(31 downto 0);

begin
     m1:mul_ip port map(a,b,clk,answer1);
     a1:add_ip port map(a,"01000000000000000000000000000000",clk,answer2);
     a2:add_ip port map(answer1,answer2,clk,answer3);
     m2:mul_ip port map(answer3,a,clk,c);
end architecture;

In the first program (using the package), I will get the result in 1 rising clock edge. But the second program (using IP core) needs 4 clock rising edges. How can I ensure result in 1 clock cycle and still using IP cores?

 

 

Please reply me.

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