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Contributor
Contributor
275 Views
Registered: ‎10-29-2018

for loops, always blocks, synthesis, implementation, and you...

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Since you cannot put a for-loop or genvar loop within an always block (someone please let me know immediately if this is false),

 

I went ahead and created the Verilog module attached here. When I synthesize and run implementation it sometimes passes

and sometime fails implementation depending on code changes *not* within this module which is weird. It seems to pass synthesis always.

The issue is the variable "one_row". At times the implementation run will give me errors like the one pasted below. Anyone know the right way to do this?

[DRC MDRV-1] Multiple Driver Nets: Net core_/data_flow_wrapper/dataflow_i/panel_bits/inst/one_row[0] has multiple drivers: core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk1[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk9[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk10[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk4[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk8[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk5[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk7[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk2[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk11[0].one_row_reg[0]/Q, core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk3[0].one_row_reg[0]/Q, and core_/data_flow_wrapper/dataflow_i/panel_bits/inst/genblk6[0].one_row_reg[0]/Q.

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Scholar u4223374
Scholar
229 Views
Registered: ‎04-26-2015

Re: for loops, always blocks, synthesis, implementation, and you...

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(1) You can certainly have a for loop inside an always block.

 

(2) As above, you cannot write to a register (or anything else) from multiple always blocks.

 

(3) Changes elsewhere in the code may well result in Vivado optimizing away substantial portions of this module (eg. if you don't use the output, Vivado will just get rid of it). This can result in "problematic" parts (like registers that are written from multiple locations) being deleted, so they don't cause problems in implementation.

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Voyager
Voyager
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Registered: ‎02-01-2013

Re: for loops, always blocks, synthesis, implementation, and you...

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A reg cannot be assigned a value in multiple always blocks. You're assigning the reg named one_row a value in many different always blocks.

-Joe G.

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Moderator
Moderator
234 Views
Registered: ‎07-21-2014

Re: for loops, always blocks, synthesis, implementation, and you...

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@threedtramp

Thanks for posting your query on Synthesis board. Please do not dumplicate the queries:
https://forums.xilinx.com/t5/Synthesis/for-loops-always-blocks-synthesis-implemenatation-and-you/m-p/935649/highlight/false#M29816

Thanks
Anusheel 

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Scholar u4223374
Scholar
230 Views
Registered: ‎04-26-2015

Re: for loops, always blocks, synthesis, implementation, and you...

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(1) You can certainly have a for loop inside an always block.

 

(2) As above, you cannot write to a register (or anything else) from multiple always blocks.

 

(3) Changes elsewhere in the code may well result in Vivado optimizing away substantial portions of this module (eg. if you don't use the output, Vivado will just get rid of it). This can result in "problematic" parts (like registers that are written from multiple locations) being deleted, so they don't cause problems in implementation.

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