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betontalpfa
Explorer
Explorer
1,878 Views
Registered: ‎10-12-2018

get_cells [Vivado 12-180] No cells matched

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Hi,

I want to set false path towards my metastability filters with the following constraint:

 

set false_pins [get_cells inst_ps7_subsystem/aurora_ctrl_0/U0/q_*_meta1*]
set_false_path -to $false_pins

I have read that I must give these constraints to syntheis step in this guide.

 

But I get the following warning during synthesis:

 

[Vivado 12-180] No cells matched 'inst_ps7_subsystem/aurora_ctrl_0/U0/q_*_meta1*'. ["<path>.xdc":101]

But there are matched cells after the synthesis (int the Tcl console):

 

image.png

How can I get all cells that ends with 'meta1'?

How can I get a list of false paths (after synthesis)?

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avrumw
Guide
Guide
1,860 Views
Registered: ‎01-23-2009

Take a look at this post on how Vivado deals with IP during the synthesis process.

Most likely the cell you are referring to exists in an IP and hence is part of a "black box" during synthesis (so is inaccessible) - once synthesis completes, the black box is filled in, and hence the cell exists during implementation and also on the Tcl console after synthesis...

Avrum

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4 Replies
xilinxacct
Instructor
Instructor
1,877 Views
Registered: ‎10-23-2018

@betontalpfa

Did you manually type in the constraint or let the system type it for you?

If you manually types it, you should check for a typo in the name.

To avoid typos, I tend to click on the path, then right mouse click, and add the constraint that way.

Hope that helps

If so, please mark as solution accepted (Kudos also accepted :-)

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avrumw
Guide
Guide
1,861 Views
Registered: ‎01-23-2009

Take a look at this post on how Vivado deals with IP during the synthesis process.

Most likely the cell you are referring to exists in an IP and hence is part of a "black box" during synthesis (so is inaccessible) - once synthesis completes, the black box is filled in, and hence the cell exists during implementation and also on the Tcl console after synthesis...

Avrum

View solution in original post

betontalpfa
Explorer
Explorer
1,796 Views
Registered: ‎10-12-2018

Hi @avrumw

This not solved the warnings. I added the hierarchical swithc to get_cells (and I have removed the full path), to mach everytime, but I get the same warning.

 

set false_pins [get_cells -hierarchical q_*_meta1*]

I cannot eliminate the warning.

The place where the 'meta1' registers located added to my blockdesign usign the 'Add Module to Blockdesign' menu.

 

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avrumw
Guide
Guide
1,785 Views
Registered: ‎01-23-2009

Please read the post I referenced - the -hierarchical flag has nothing to do with this.

Avrum

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