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Visitor heller390
Visitor
11,751 Views
Registered: ‎02-21-2016

getting "U" in some outputs during simulation

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Hello I am new to Xilinx.Basically I am implementing a 1784 bit interleaver and deinterleaver using CCSDS algortihm.I want to check whether they are right.So i module instantiated both interleaver and deinterleaver files by writing a wrapper file and then gave some test input.Everything works fine except that I am getting 5 outputs as "UNINITIALIZED" out of 1784.I tried debugging but cant identify the problem.Please kindly help me solve the issue

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Xilinx Employee
Xilinx Employee
21,969 Views
Registered: ‎05-07-2015

Re: getting "U" in some outputs during simulation

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HI @heller390

 

This can happen in  VHDLbehavioural simulations in genreral, if one of the drivers of the signal you are monitoring is unintialized. Please  initialize them to "Z" in your RTL.. (use  :=(others => 'Z'), if it is a bus ).

 

Is the post-synth simulation working fine?

Thanks
Bharath
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Xilinx Employee
Xilinx Employee
11,745 Views
Registered: ‎07-21-2014

Re: getting "U" in some outputs during simulation

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Hi,

Are you doing behavioural simulation or post synthesis simulation? does your deisgn work in behavioural simulation?

-Shreyas
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Xilinx Employee
Xilinx Employee
21,970 Views
Registered: ‎05-07-2015

Re: getting "U" in some outputs during simulation

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HI @heller390

 

This can happen in  VHDLbehavioural simulations in genreral, if one of the drivers of the signal you are monitoring is unintialized. Please  initialize them to "Z" in your RTL.. (use  :=(others => 'Z'), if it is a bus ).

 

Is the post-synth simulation working fine?

Thanks
Bharath
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Visitor heller390
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11,679 Views
Registered: ‎02-21-2016

Re: getting "U" in some outputs during simulation

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Thanks for the reply guys.I am doing behavioural implemenatation after going through the process of checking behavioural syntax.syntax is fine.But i get some op as U.

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Visitor heller390
Visitor
11,676 Views
Registered: ‎02-21-2016

Re: getting "U" in some outputs during simulation

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Thanks for the solution.The design is working fine after initiliazing as u said.Once again thanks for helping me .

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Xilinx Employee
Xilinx Employee
11,575 Views
Registered: ‎05-07-2015

Re: getting "U" in some outputs during simulation

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HI @heller390

 

Glad to know. this happens  in VHDL  behavioural simulation.if a signal has two drivers 'U' and '1'/'0'. The resultant output will 'U'. 
You will not find this problem in post-synth simulations. 
It is a good practice initialize driver signals to 'Z' instead of leaving them unintialized in VHDL.

Thanks
Bharath
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Visitor rubana
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7,918 Views
Registered: ‎06-08-2016

Re: getting "U" in some outputs during simulation

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I have a few data lines in my program and for all the "inout" signal types i am getting uninitialised result? However, if i change these data lines to either output or input i am getting the result? Does isim not support "inout" port?

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Xilinx Employee
Xilinx Employee
7,910 Views
Registered: ‎05-07-2015

Re: getting "U" in some outputs during simulation

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HI @rubana

 

Always create new thread for your query and for more visibility.

As explained in this post, this behaviour is typical VHDL behavioural simulation of inout signals , please initialize the inout signals to "Z" value as mentioned above and try.

Thanks
Bharath
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Observer abdelkader
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Registered: ‎12-06-2011

Re: getting "U" in some outputs during simulation

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hI?

 

I am working on interleaver implementation, can you please mention a link of your project or a report about how to implement it?

 

Thank you

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