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hwlee
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Registered: ‎12-20-2020

glbl is not declared during XADC.v synthesize in ISE 14.5

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Hi, I'm trying to run synthesize for Xilinx XADC.v which is located in unisims folder. However, there was an error occurred during synthesize. 

"ERROR:HDLCompiler:69 - Line 344: <glbl> is not delcared.

Anyone have the solution for this ?

Thanks in Advance.

 

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hongh
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Registered: ‎11-04-2010

The files under unisims dir are used for simulation. Please avoid using it in synthesis. The primitives is FPGA can be recognized in XST automatically.

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hongh
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Registered: ‎11-04-2010

The files under unisims dir are used for simulation. Please avoid using it in synthesis. The primitives is FPGA can be recognized in XST automatically.

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hwlee
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Registered: ‎12-20-2020

Hi, 

Yes, you're right. Files under unisims dir are not supposed to used for simulation/ synthesize. Problem has solved by not synthesize the XADC.v code. Instead, copy over the XADC instantiation template from language template panel, and paste in inside the ADC top level module code (which you create yourself) with all ports declared which corresponding to the ports available from XADC instantiation template. 

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