08-13-2019 10:50 AM
hello, I'm using the gtwizard 3.6 for an Artix7 design. If you dive into the hierarchy, there's a signal 'gt0_drp_busy_out'. I need to use this signal for another part of my design. however, that signal is not brought out to the upper hierarchy ports for some reason. I named the gtwizard "gtwizard_8ch_bot" and tried to do the following:
assign gt0_drp_busy_out = gtwizard_8ch_bot_support_i.inst.gtwizard_8ch_bot_init_i.gt0_drp_busy_out;
this works in simulation, but when I try to synthesize, it complains that it cannot resolve the hierarchical name. I think this means that synthesis optimized out gt0_drp_busy_out.
how can I use this signal?
08-19-2019 04:17 AM
Hi @mvalvo ,
If it is optimized out then synthesis log will show it. Provide synthesis log to evaluate.
And which Vivado version are you using?
Hierarchical names are supported from Vivado 2017.3 onwards. If you are using older version then it will throw an error as you saw.
08-19-2019 10:05 PM
Hi @mvalvo ,
>>does that mean that I shouldn't get that error?
Can you elaborate more with steps on what you did and face this error? So i can reproduce this error at my end with gt wizard and try to find out the root cause.
08-20-2019 09:41 AM - edited 08-20-2019 09:42 AM