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sdbzlh
Adventurer
Adventurer
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Registered: ‎02-26-2009

[help] "Keep hierarchy" leads to a failure of synthesis

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In my design, when setting "keep hierarchy" to "yes" in XST property, it fails because of several multi-driven signals, while succeed when setting it to "no".

And the signals said to be driven by several sources are obviously unrelated to the sources.That is, A,B are said to be the sources of C, A has something to do with C, but B has not a little thing to do with C.It's rediculous.

:smileytongue:

Can anybody help me and point out where I am wrong? Thank you very much!

Regards,
Hu LI
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sdbzlh
Adventurer
Adventurer
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Registered: ‎02-26-2009
Oh my God! After I fixed some functional errors of my code, synthesis has passed successfully even when "keep hierarchy" is "no".
Regards,
Hu LI

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evgenis1
Advisor
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Registered: ‎12-03-2007

How complex is your design. Doesn it include any large Xilinx cores like MIG. 

I was also getting strange errors when tried to synthesize a design with MIG and "keep hierarchy" = "yes. I've never resolved it and kept using "keep hierarchy" = "no".

 

Another question. Why do you want to use "keep hierarchy"="yes" in the first place.

 

OutputLogic 

 

 

 

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sdbzlh
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Registered: ‎02-26-2009

There is a PCI Express Core in my design.

 I don't want to use "keep hierarchy" = "yes", because this will cause a decrease of ability of my design. But in this case, if "no" there will be a failure, so I have to use "yes".

Any other idea?

Regards,
Hu LI
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evgenis1
Advisor
Advisor
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Registered: ‎12-03-2007

Well, have you talked with Xilinx TechSupport about this error ?

 

XST documentation on "Keep Hierarchy" says that :

 

  " XST can flatten the design to obtain better results by optimizing entity or module boundaries. Very often, merging the hierarchy blocks improves the fitting results (fewer PTerms and device macrocells, better frequency) because the optimization processes (collapsing, factorization) are applied globally on the entire logic. "

 

I'm still not sure exactly what abilities of your design will decrease.

 

 

  OutputLogic

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sdbzlh
Adventurer
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Registered: ‎02-26-2009

As you say, if "yes", XST will not flatten design to optimize. I think this is just like XST will optimize the design on each part of it. But only that is not enough. For example, if you have a lot of good components, you'll not get a 100% good system when you use the components to form a whole system. So optimize the design on the component level when "yes" will decrease the performance, in my opinion.

What's your opinion?

Regards,
Hu LI
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evgenis1
Advisor
Advisor
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Registered: ‎12-03-2007

Sorry, but I'm still missing your point. What do you mean by "performance" ?

Functionally, the design with "yes" and "no" options is the same. As the XST documentation explains, flattening the design makes it easier to meet timing.

 

 

OutputLogic 

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evgenis1
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Registered: ‎12-03-2007

I found this Xilinx Answer Record about KEEP_HIERARCHY

http://www.xilinx.com/support/answers/17693.htm

 


OutputLogic.

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sdbzlh
Adventurer
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Registered: ‎02-26-2009
Hm, thank you. I mean "timing performance". Last time when designing another project, if I choose "yes", timing will be bad enough, but "yes" will be fine.
Regards,
Hu LI
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sdbzlh
Adventurer
Adventurer
10,186 Views
Registered: ‎02-26-2009
Oh my God! After I fixed some functional errors of my code, synthesis has passed successfully even when "keep hierarchy" is "no".
Regards,
Hu LI

View solution in original post

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