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tchin123
Voyager
Voyager
1,965 Views
Registered: ‎05-14-2017

hierarchical name with MARK_DEBUG

Does hierarchical naming convention work with Mark_debug:

If I have a design called TOP and it contains a instance called Decode_instA and inside this another instance called CPU_instB.

Within this module there is a signal/wire called XYZ. Will Vivado accept this when declared within TOP ?

 

(* mark_debug = "true" *) wire Decode_instA/CPU_instB/XYZ;

 

I try this out and it didn't work.

Does this work or is the syntax different?

 

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hpoetzl
Voyager
Voyager
1,954 Views
Registered: ‎06-24-2013

Hey @tchin123,

 

Hierarchical name support is not that good in Vivado yet.

 

Why not do it in TCL where you have access to all the defined nets, pins and ports?

 

Best,

Herbert

-------------- Yes, I do this for fun!
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vijayak
Xilinx Employee
Xilinx Employee
1,950 Views
Registered: ‎10-24-2013

Hi @tchin123

Check the below document for supported list.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_2/ug901-vivado-synthesis.pdf page 228

Thanks,Vijay
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vemulad
Xilinx Employee
Xilinx Employee
1,899 Views
Registered: ‎09-20-2012

Hi @tchin123

 

You can apply the mark_debug attribute on hierarchical net names from XDC file.

Thanks,
Deepika.
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