08-15-2017 07:59 PM
Does hierarchical naming convention work with Mark_debug:
If I have a design called TOP and it contains a instance called Decode_instA and inside this another instance called CPU_instB.
Within this module there is a signal/wire called XYZ. Will Vivado accept this when declared within TOP ?
(* mark_debug = "true" *) wire Decode_instA/CPU_instB/XYZ;
I try this out and it didn't work.
Does this work or is the syntax different?
08-15-2017 08:31 PM
Hierarchical name support is not that good in Vivado yet.
Why not do it in TCL where you have access to all the defined nets, pins and ports?
08-15-2017 08:52 PM
Check the below document for supported list.
08-16-2017 04:22 AM
You can apply the mark_debug attribute on hierarchical net names from XDC file.