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luoyanghero
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Registered: ‎11-24-2016

how can I change the ram resource type when instance different size?

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I use vivado 2016.03. I have a ram model as follow, this model will instance many times with different parameters. such as SIZE=8, 16, 32, 40, 100, 200, 500, ... 

In default synthesis settings, I tested , when SIZE < 256; vivado will use register to build the ram model, when SIZE>256 vivado will use block ram to build the ram model.

My question is, how can I change the setting, for example, when SIZE>50 use block ram. 

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luoyanghero
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Registered: ‎11-24-2016

Just use coregen, it is the best way to control use which utilization.

View solution in original post

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

these might help

 

https://www.xilinx.com/support/answers/46515.html

 

And here page 76

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug953-vivado-7series-libraries.pdf

 

if you instantiate the macro , then you can control this , 

 

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graces
Moderator
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Registered: ‎07-16-2008

You can use RAM_STYLE attribute to instruce the Vivado synthesis tool on how to infer memory.

Accepted values are:
• block: Instructs the tool to infer RAMB type components.
• distributed: Instructs the tool to infer the LUT RAMs.
• register: Instructs the tool to infer registers instead of RAMs.
• ultra: Instructs the tool to use the Zynq UltraScale+ URAM primitives.

 

e.g.

(* ram_style = “block”*) reg signed [14:0]   memory[SIZE]; 

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luoyanghero
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Registered: ‎11-24-2016

I made a test as your description, but is not my expect.

I use IP core-gen generate 4 different type fifo(‘block ram’, ‘distributed ram’, ‘shift register’, ‘builtin fifo’), after synthesis and implementation, the resource is my expect: ‘builtin fifo’ and ‘block ram’ use ‘Block RAM Tile’ resources, ‘distributed ram’ and ‘shift register’ use LUT resources.

Then I use my ‘SYN_FIFO’ module, and add ‘(* ram_style = *)’ to my register memory define, and instance them to different depth from 16 to 1024, they are all use LUT resources, no ‘Block RAM’ resouces.

This is my SYN_FIFO_S code:

`ifndef DLY
`define DLY	1
`endif
module SYN_FIFO_S(
    clk_bus, brst_n, start_rst, fifo_wr, fifo_wdata, fifo_rd, 
    fifo_full, almost_full, fifo_rdata, fifo_emp);
parameter	DEPTH = 8;
parameter	AW	  = 3;
parameter	DW	  = 32;

input					clk_bus;
input					brst_n;
input					start_rst;

input					fifo_wr;
input[DW-1:0]			fifo_wdata;
output					fifo_full;
output					almost_full;

input					fifo_rd;
output[DW-1:0]			fifo_rdata;
output					fifo_emp;

reg  [AW:0]				fifo_cnt;    
reg  [AW-1:0]           fifo_raddr;    
(* ram_style = "register"*)    reg  [DW-1:0]     fifo_reg[0:DEPTH-1];    
reg  [AW-1:0]           fifo_waddr;    
wire [DW-1:0]			fifo_rdata;    
wire					fifo_emp;
wire					fifo_full;
always @ (posedge clk_bus or negedge brst_n) begin
	if (~brst_n)
		fifo_cnt[AW:0] <= #`DLY {(AW+1){1'b0}};
	else if (start_rst)
		fifo_cnt[AW:0] <= #`DLY {(AW+1){1'b0}};
	else if (fifo_rd && fifo_wr)
		fifo_cnt[AW:0] <= #`DLY fifo_cnt;
	else if (fifo_rd)
		fifo_cnt[AW:0] <= #`DLY fifo_cnt - 1'b1;
	else if (fifo_wr)
		fifo_cnt[AW:0] <= #`DLY fifo_cnt + 1'b1;
end

always @ (posedge clk_bus or negedge brst_n) begin
	if (~brst_n)
		fifo_waddr[AW-1:0] <= #`DLY {AW{1'b0}};
	else if (start_rst)
		fifo_waddr[AW-1:0] <= #`DLY {AW{1'b0}};
	else if (fifo_wr)
		fifo_waddr[AW-1:0] <= #`DLY (fifo_waddr == DEPTH-1'b1) ? {AW{1'b0}} : fifo_waddr + 1'b1;
end

always @ (posedge clk_bus or negedge brst_n) begin
	if (~brst_n)
		fifo_raddr[AW-1:0] <= #`DLY {AW{1'b0}};
	else if (start_rst)
		fifo_raddr[AW-1:0] <= #`DLY {AW{1'b0}};
	else if (fifo_rd)
		fifo_raddr[AW-1:0] <= #`DLY (fifo_raddr == DEPTH-1'b1) ? {AW{1'b0}} : fifo_raddr + 1'b1;
end

assign fifo_rdata[DW-1:0] = fifo_reg[fifo_raddr];

always @ (posedge clk_bus) begin
	if (fifo_wr)
		fifo_reg[fifo_waddr] <= #`DLY fifo_wdata;
end

assign fifo_emp  = (fifo_cnt == 0);
assign fifo_full = (fifo_cnt == DEPTH);
assign almost_full = (fifo_cnt >= DEPTH - 1);


endmodule

in SYN_FIFO_M code, everything is same with SYN_FIFO_S except this:

(* ram_style = "distributed"*) reg  [DW-1:0]     fifo_reg[0:DEPTH-1];    

in SYN_FIFO_L code, everything is same with SYN_FIFO_S except this:

(* ram_style = "block"*)       reg  [DW-1:0]     fifo_reg[0:DEPTH-1];    

This is my implementation resource result:

ram-resource.png

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luoyanghero
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1,039 Views
Registered: ‎11-24-2016

Just use coregen, it is the best way to control use which utilization.

View solution in original post

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