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Voyager
Voyager
2,930 Views
Registered: ‎03-18-2008

how not to be extracted RAM,only register array?

like synplify:

 

reg  [31:0] memory  [8:0]   /* synthesis syn_ramstyle="registers" */;

 

I hope it will be register array,not any ram. Or,how not to be extracted RAM,only register by XST?

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Xilinx Employee
Xilinx Employee
2,922 Views
Registered: ‎09-20-2012

Hi,

 

You can set ram_extract to NO. This attribute can be applied globally via synthesis settings. or it can be applied on specific signal/module/entity in HDL. Refer to page-412 0f http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf

 

The page-465 of this guide gives synplify equivalent attributes in ISE, see below

 

Capture.JPG

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
2,916 Views
Registered: ‎08-02-2007

Hi

This looks to be a similar question given in the below link

http://forums.xilinx.com/t5/Synthesis/how-to-synthesize-a-memory-with-register-style-not-blockram/m-p/392471/highlight/false#M9740

If yes can we have one of the post marked as accepted solution if the question has been answered?

Hem
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