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9,972 Views
Registered: ‎12-04-2013

how to avoid trimming of signals in inner module

HI all,

  i have several blocks in my design. there in one intrnal control blocks, the output of that control block will have some address signal(this address hard coded with different names inside the block will assign addr names with output address depends the mode it will work ) in that process only few bits are changing remainig are continuesly at zero value. so synthesis tool is trimming out all the constant signal in the output address signal but i want to preserve taht signal . can you please tell me how to save that signals from trimming    

 

 

thanks

vinodh

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12 Replies
Xilinx Employee
Xilinx Employee
9,966 Views
Registered: ‎07-11-2011

Re: how to avoid trimming of signals in inner module

Hi,

 

Is this ISE or Vivado?

you can use KEEP attribute.

 

Please check these links

 

http://forums.xilinx.com/t5/Synthesis/How-to-avoid-signal-optimizing-in-synthesis/td-p/76056

 

http://forums.xilinx.com/t5/Vivado-TCL-Community/Setting-KEEP-HIERARCHY-or-DONT-TOUCH-properties-from-TCL-XDC/td-p/281800

 

 

Regards,

Vanitha

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Moderator
Moderator
9,965 Views
Registered: ‎01-16-2013

Re: how to avoid trimming of signals in inner module

Hello,

Please use KEEP attribute.

Refer UG http://www.xilinx.com/support/documentation/sw_manuals_j/xilinx2014_1/ug901-vivado-synthesis.pdf (Page # 43)

Thanks,
Yash

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Xilinx Employee
Xilinx Employee
9,961 Views
Registered: ‎11-28-2007

Re: how to avoid trimming of signals in inner module

Hi Vinodh,

 

there are 2 constraints that can help you:

KEEP and DONT_TOUCH.

 

KEEP is only used during synthesis.

DONT_TOUCH is preserved and kept throughout the flow.

 

see UG901-Vivado-synthesis:

screenshot_006.jpg

 

 

Best regards

Dries

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Xilinx Employee
Xilinx Employee
9,958 Views
Registered: ‎11-28-2007

Re: how to avoid trimming of signals in inner module

For ISE, the equivalent / strongest constraint is S(AVE_NET).

 

See the ISE constraints userguide for more info.

 

 

Best regards

Dries

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9,952 Views
Registered: ‎12-04-2013

Re: how to avoid trimming of signals in inner module

trimming signal is output signal . can you please give syntax for for keep or donot_touch???

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Moderator
Moderator
9,948 Views
Registered: ‎01-16-2013

Re: how to avoid trimming of signals in inner module

Hello,

You also can refer UG 901 provided by me. for more info and Syntax.

Also Dries already provided the syntax. Its same as present in UG 901.

Thanks,
Yash

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9,941 Views
Registered: ‎12-04-2013

Re: how to avoid trimming of signals in inner module

i am using ISE for spartan -3a DSP. all examples given for wires and registers, but i need for OUTPUT signal (i am getting error when use same syntax as wire for output signal). so how to peserve that output singnal ????

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Moderator
Moderator
9,929 Views
Registered: ‎01-16-2013

Re: how to avoid trimming of signals in inner module

Hello,

Can you please post your code? I will check and let you know.

Thanks,
Yash
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Xilinx Employee
Xilinx Employee
9,922 Views
Registered: ‎02-16-2014

Re: how to avoid trimming of signals in inner module

Hi Vinodh,

 

KEEP preserves the existence of the designated signal in the final netlist,but not the final netlist.

 

As dries mentioned SAVE constraint  may prevent the trimming of logic connected to that signal.

 

Try applying SAVE constraint on the signal which drives OUTPUT signal. This may help.

 

The syntax is mentioned below.

For more details refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/cgd.pdf

 

Capture.PNG

 

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Historian
Historian
5,992 Views
Registered: ‎02-25-2008

Re: how to avoid trimming of signals in inner module


@vinodhcherukuri1990@gmail.com wrote:

. so synthesis tool is trimming out all the constant signal in the output address signal but i want to preserve taht signal 


WHY?

----------------------------Yes, I do this for a living.
Highlighted
5,981 Views
Registered: ‎12-04-2013

Re: how to avoid trimming of signals in inner module

module controller (

// ports for master1 interface
input [31:0] hrdata_master1_controller,
input [1:0] hresp_master1_controller,
input hready_resp_master1_controller,

output reg [31:0] haddr_master1_controller,
output reg hwrite_master1_controller,
output reg hready_master1_controller,
output reg [2:0] hburst_master1_controller,
output reg hsel_master1_controller,
output reg [1:0] htrans_master1_controller,
output reg [2:0] hsize_master1_controller,
output reg [31:0] hwdata_master1_controller,
// ports for master2 interface

input [31:0] ahb_master2_hrdata_controller,
input ahb_master2_hgrant_controller,
input ahb_master2_hready_controller,
input ahb_master2_hresp_controller,

output reg [31:0] ahb_master2_haddr_controller,
output reg ahb_master2_hwrite_controller,
output reg [2:0] ahb_master2_burst_controller,
output reg [1:0] ahb_master2_htrans_controller,
output reg [2:0] ahb_master2_hsize_controller,
output reg [31:0] ahb_master2_hwdata_controller,
output reg ahb_master2_hbusreq_controller,
output reg ahb_master2_hlock_controller,
output reg [3:0] ahb_master2_hprot_controller,

// temp ports
//output reg [127:0] enc_data,
//output reg ready_enc_data,
//input ready_second_init,

// clock and reset pins
input clock,
input reset,
//Ports for Manually exported pins
input random_number_ready,
input aes_valid
//input [127:0] external_key

)

 

 

here i have to save "haddr_master1_controller" signal from trimming . how?????? 

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Moderator
Moderator
5,973 Views
Registered: ‎01-16-2013

Re: how to avoid trimming of signals in inner module

Hello,

Below is the syntax for KEEP in verilog.
(*KEEP = "TRUE"*) output reg [1:0] signal_name

Thanks,
Yash
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