05-08-2014 04:17 AM
i have several blocks in my design. there in one intrnal control blocks, the output of that control block will have some address signal(this address hard coded with different names inside the block will assign addr names with output address depends the mode it will work ) in that process only few bits are changing remainig are continuesly at zero value. so synthesis tool is trimming out all the constant signal in the output address signal but i want to preserve taht signal . can you please tell me how to save that signals from trimming
05-08-2014 04:30 AM
Is this ISE or Vivado?
you can use KEEP attribute.
Please check these links
05-08-2014 04:30 AM - edited 05-08-2014 04:34 AM
05-08-2014 04:32 AM
there are 2 constraints that can help you:
KEEP and DONT_TOUCH.
KEEP is only used during synthesis.
DONT_TOUCH is preserved and kept throughout the flow.
05-08-2014 04:33 AM
For ISE, the equivalent / strongest constraint is S(AVE_NET).
See the ISE constraints userguide for more info.
05-08-2014 04:38 AM
trimming signal is output signal . can you please give syntax for for keep or donot_touch???
05-08-2014 04:41 AM - edited 05-08-2014 04:43 AM
You also can refer UG 901 provided by me. for more info and Syntax.
Also Dries already provided the syntax. Its same as present in UG 901.
05-08-2014 04:52 AM
i am using ISE for spartan -3a DSP. all examples given for wires and registers, but i need for OUTPUT signal (i am getting error when use same syntax as wire for output signal). so how to peserve that output singnal ????
05-08-2014 05:49 AM
KEEP preserves the existence of the designated signal in the final netlist,but not the final netlist.
As dries mentioned SAVE constraint may prevent the trimming of logic connected to that signal.
Try applying SAVE constraint on the signal which drives OUTPUT signal. This may help.
The syntax is mentioned below.
For more details refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/cgd.pdf
05-08-2014 09:45 AM
. so synthesis tool is trimming out all the constant signal in the output address signal but i want to preserve taht signal
05-08-2014 08:39 PM
module controller (
// ports for master1 interface
input [31:0] hrdata_master1_controller,
input [1:0] hresp_master1_controller,
output reg [31:0] haddr_master1_controller,
output reg hwrite_master1_controller,
output reg hready_master1_controller,
output reg [2:0] hburst_master1_controller,
output reg hsel_master1_controller,
output reg [1:0] htrans_master1_controller,
output reg [2:0] hsize_master1_controller,
output reg [31:0] hwdata_master1_controller,
// ports for master2 interface
input [31:0] ahb_master2_hrdata_controller,
output reg [31:0] ahb_master2_haddr_controller,
output reg ahb_master2_hwrite_controller,
output reg [2:0] ahb_master2_burst_controller,
output reg [1:0] ahb_master2_htrans_controller,
output reg [2:0] ahb_master2_hsize_controller,
output reg [31:0] ahb_master2_hwdata_controller,
output reg ahb_master2_hbusreq_controller,
output reg ahb_master2_hlock_controller,
output reg [3:0] ahb_master2_hprot_controller,
// temp ports
//output reg [127:0] enc_data,
//output reg ready_enc_data,
// clock and reset pins
//Ports for Manually exported pins
//input [127:0] external_key
here i have to save "haddr_master1_controller" signal from trimming . how??????
05-09-2014 12:09 AM