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Observer
Observer
1,060 Views
Registered: ‎03-05-2018

how to connect 4 bidirectional signal into 2 lines

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Hello everyone,

 

i need connect 4 i2c signal

scl1,scl2  into single scl line

sda1,sda2 into  single sda line

 

i have no. of experiments but i failed ..

 

my data flows in only one direction not vice versa .

in synthesis tool mixed driver error comes.

hoiw can i resoilve this problem using vhdl code ..

 

 

plz reply...

 

Thank you...........

 

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970 Views
Registered: ‎01-22-2015

aishwaryaakul@ 

For the I2C connections with the FPGA, you should specify the ports in VHDL to be “inout” as yangc says and you should use the FPGA buffer call IOBUF.  

B9D60F0D-E856-4CF1-9EFA-1A38C384B7F0.jpeg

It is possible to infer IOBUF by writing your VHDL in a special way.  However, you many find it easier to instantiate IOBUF into your design as described in UG953.

Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-27-2019

Hi aishwaryaakul@ ,

  Sorry , I can't understand your request. But for:

                                                my data flows in only one direction not vice versa .

                                                in synthesis tool mixed driver error comes.

I think you should set SCL and SDA ports as inout rather than just input or output. 

Yang

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Observer
Observer
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Registered: ‎03-05-2018

Thank for reply

 

But I want these signal flows in both directions....

See below signal I want such behaviour of signal data all signal inout

When I write code in vhdl .I got multiple

I got error. Mixed driver type

 

Scl<= scl1;

Scl <= scl2;

Scl2<= scl;

Scl1<= scl;

 

Same for sda signal also ..

 

Plz help me on this . topic ...

How to write vhdl code for such behaviour..

 

 

Thank you

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Teacher
Teacher
998 Views
Registered: ‎06-16-2013

Hi aishwaryaakul@ 

 

I don't know how to describe open-drain by VHDL.

But, here is description of open-drain by Verilog HDL.

 

// Output

assign scl = (internal_scl) ? 1'bZ: 1'b0;

assign sda = (internal_sda) ? 1'bZ: 1'b0;

 

Also, I suggest you to understand open-drain, too.

 

Best regards,

 

 

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971 Views
Registered: ‎01-22-2015

aishwaryaakul@ 

For the I2C connections with the FPGA, you should specify the ports in VHDL to be “inout” as yangc says and you should use the FPGA buffer call IOBUF.  

B9D60F0D-E856-4CF1-9EFA-1A38C384B7F0.jpeg

It is possible to infer IOBUF by writing your VHDL in a special way.  However, you many find it easier to instantiate IOBUF into your design as described in UG953.

Mark

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Observer
Observer
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Registered: ‎03-05-2018

Thank you....

 

Do .you have example code regarding iobuf.....

BeacaBe I searched on net but I didn't got exactly what I want....

 

Plz share.... some example code fif better understanding

 

 

 

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Explorer
Explorer
954 Views
Registered: ‎06-25-2014

In Vivado there are language templates where if you look under:

 

VHDL->Synthesis Constructs->Coding Examples->Bi-Directional IO

You will find what you are looking for

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Registered: ‎01-22-2015
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Guide
Guide
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Registered: ‎01-23-2009

Here are links to a couple of other I2C related threads which give reasons why you do not want to try and do a I2C MUX in an FPGA.

https://forums.xilinx.com/t5/General-Technical-Discussion/implementing-vhdl-I2C-MUX-in-CPLD-VHDL/m-p/369423#M15567

https://forums.xilinx.com/t5/Welcome-Join/joining-bidirectional-pins/m-p/300045#M3448

Avrum

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Registered: ‎01-22-2015

@avrumw  - thank you!

@all others

I agree with all of Avrum’s concerns about using IOBUF to approximate the operation of lines (SDA or SCL) used in an I2C communications interface.  However, I have successfully used IOBUF for some I2C communications.

As Avrum explains in his referenced threads, I2C devices are supposed to have an open-drain (aka pass-transistor) connection to the SDA/SCL lines – and both lines have pull-up resistors.  Thus, I2C devices can either drive the line low (by activating the pass-transistor) or allow the line to pulled high by the pull-up resistors (and by deactivating the pass-transistor).  Note that I2C devices cannot “electronically battle” each other in the way that two standard logic gates can when their outputs are tied together (eg. a high-output connected to a low-output).

The “electronic battle” is the reason you should not have two FPGAs (using IOBUF) on a single I2C communication interface.  That is, if the two IOBUFs are trying to drive the line in different directions then IOBUF damage may result. Although, carefully placing a small series resistor in the line can prevent damage and should allow reduced-speed I2C to continue.

Here is the situation where I made the FPGA (using IOBUFs) talk to multiple I2C devices on a single I2C interface:

  • Slow-speed clock, SCL, (~10 kHz)
  • FPGA is the I2C master (ie. it initiates all I2C communication and it always controls the SCL line)
  • SCL clock-stretching is not needed

Also, in my situation, I used the oversampled-interface technique that I described <here> for working with I2C.  This technique (also known as bit-banging) uses a FPGA generated clock, CLKF, that is much faster (mine was 100x) than SCL.  My HDL counted cycles of CLKF to toggle SCL at the correct speed.  My HDL also counted cycles of CLKF in order to read/write a bit from/to the SDA at the "right time" (ie. the interface passed timing analysis by design).  Note that from the HDL viewpoint, both SCL and SDA are “signals” (ie. SCL is not an “true” clock in the FPGA sense).  Also, I placed a synchronizer (eg. 2-flip-flop type found in IDDR) on the “O” output of the IOBUF for the SDA line to mitigate metastability.  Finally, I locked the registers used to send SCL and SDA into the FPGA’s IOB.

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Guide
Guide
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Registered: ‎01-23-2009

markg@prosensing.com 

Just to be clear - I am in no way implying that you can't use an FPGA for an I2C master or an I2C slave - both of those are perfectly implementable, even including all the details of clock stretching, multi-mastering, etc... The "open drain" functionality of the I2C buffers are easlily accomplished using IOBUF primitives and driving either 0 or Hi-Z.

What can't be done is having an FPGA as an I2C MUX, or any place where an FPGA is placed between an I2C master and an I2C slave that are supposed to be on the same bus (or for that matter, even multiple masters). The I2C bus requires a real "wire" connection between all masters and slaves on the same bus, and there is no way to really emulate this with the FPGA - all devices that do this (off the shelf I2C MUX chips) are based on pass transistors, which can't be done in an FPGA.

Avrum

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