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Visitor wyh@521
Visitor
431 Views
Registered: ‎01-15-2019

how to find most frequent element in an array in verilog code

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I  want to get the most frequent element in an array, for example , an array [1,2,1,3,1,4,1,5], the most frequent element is 1. but how to write the code ?

I referred other language to find the most frequent element , if have any error ,please tell me. 

 

wire [21:0] A  [0:7]; 
reg [16:0] curr_count=1;
reg [16:0] max_count=1;
reg [16:0] res= A[0];

integer i;
always @ (posedge CLK )
begin
if (RST_X)
begin
for(i=0; i<7; i=i+1)
begin
curr_count <= 0;
end
end

else if ( A[i]==A[i-1])
begin

curr_count <= curr_count+1;
end

else if ( curr_count> max_count)
begin

max_count <= curr_count;
res <= A[i - 1];
end

end

Im not sure the following syntax.

//else if ( A[i]==A[i-1])
begin

curr_count <= curr_count+1;
end//

I think this syntax just stated to compare with Whether the adjacent numbers are equal.

who can help me to correct this code ?

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1 Solution

Accepted Solutions
Scholar jmcclusk
Scholar
377 Views
Registered: ‎02-24-2014

Re: how to find most frequent element in an array in verilog code

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What you need is called a Histogram function..   After computing the histogram, then it's a matter of finding the histogram index with the highest value.

Here is an example of VHDL that implements a histogram function.   you can then add an output stage that finds the peak value of the histogram.

Now of course your target language is verilog, but this some elbow grease, you should be able to convert from VHDL to verilog.

good luck!

John

 

Don't forget to close a thread when possible by accepting a post as a solution.
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1 Reply
Scholar jmcclusk
Scholar
378 Views
Registered: ‎02-24-2014

Re: how to find most frequent element in an array in verilog code

Jump to solution

What you need is called a Histogram function..   After computing the histogram, then it's a matter of finding the histogram index with the highest value.

Here is an example of VHDL that implements a histogram function.   you can then add an output stage that finds the peak value of the histogram.

Now of course your target language is verilog, but this some elbow grease, you should be able to convert from VHDL to verilog.

good luck!

John

 

Don't forget to close a thread when possible by accepting a post as a solution.
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