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Visitor
Visitor
348 Views
Registered: ‎07-10-2018

how to generate 4 MHz clock from 2 MHz clock in FPGA

I need to generate 4 Mhz clock from 2 MHz clock . I checked clocking wizard/MMCM/PLL , but there input clock range start from 10 MHz.

I had read about using rising and falling edge detectors but they fail to give 50% duty cycle.

can DDS(direct digital synthesizer ) convert 2MHz clock frequency into 4MHz frequency??

what are the other methods to do that??

 

Regards

Ankit

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Explorer
Explorer
335 Views
Registered: ‎04-19-2018

Re: how to generate 4 MHz clock from 2 MHz clock in FPGA

 

2 MHz.... what is that today? I remember when 4 MHz was the standard crystal frequency for 8-bit microcontrollers... those days are gone. 

I suppose your FPGA will have some decent frequency (> 20 M) input clock. just divide it and create your 4 and 2 M, instead of doubling the slow one.

I think any other route is going to be stupidly overcomplicated. All you need is a 10, 20 MHz oscillator, one input pin (no diff needed at that freq) and the MMCM. Think simple.

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Visitor
Visitor
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Registered: ‎07-10-2018

Re: how to generate 4 MHz clock from 2 MHz clock in FPGA

@satguy 

The 2 Mhz clock is generated from the input data using the clock recovery algorithm. I require one 4 MHZ clock that must be synchronize to this 2 MHz clock. If i use arty board clock to generate 4 MHz than both clock would not be synchronized. and i don't know how to synchronize/align two clocks generated from different sources.

So I thought it would be better if I can generate 4 MHz clock from my original 2 MHZ clock .

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Adventurer
Adventurer
220 Views
Registered: ‎05-23-2018

Re: how to generate 4 MHz clock from 2 MHz clock in FPGA

Why does your clock recovery algorithm recover a clock for such a small frequency? I usually generate a clock enable that's as close to the recovered edge as possible in a faster clock. Then use that clock with the clock enable to recover the data.

Usually, you'll need to oversample your data anyway to recover the clock. You could then pick the most stable part of the bit for the fast clock enable. 

For an advanced version for really high data rates, check out xapp523: https://www.xilinx.com/support/documentation/application_notes/xapp523-lvds-4x-asynchronous-oversampling.pdf

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Visitor
Visitor
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Registered: ‎07-10-2018

Re: how to generate 4 MHz clock from 2 MHz clock in FPGA

@klasha 

 

The clock recovery algorithm which I am using is mentioned in xilinx application note XAPP868 (https://www.xilinx.com/support/documentation/application_notes/xapp868.pdf ).

Is there any way I can also generate 4MHz from this algo?

 

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Scholar
Scholar
155 Views
Registered: ‎05-21-2015

Re: how to generate 4 MHz clock from 2 MHz clock in FPGA

@ankitkes2,

It is unfortunate that you posted so many copies of the same question to so many different parts of the forum, otherwise others might notice that I had answered this question alread here.  The answer I provided included using a phase detector and tracking loop, much like the XAPP outlined above.  The biggest difference between the XAPP example above and the example I outlined are the licenses in the example code.  Do note, when using Xilinx's license, that you are not allowed to benchmark their performance, use their code to develop any competing system, or distribute their design in any form other than binary form.  These restrictions to not apply to the example design I provided.

Enjoy!

Dan

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