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Visitor milan.km
Visitor
8,786 Views
Registered: ‎11-12-2015

how to make the synthesizer work with a clock

hi 

i wrote a vhdl code and I have three clks as clk,clk2x,clk4x in my code. when I synthesize the code i have this line in report

Timing constraint: Default period analysis for Clock 'clk4x'

how could I make it give clk as default?

thanks

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17 Replies
Instructor
Instructor
8,780 Views
Registered: ‎08-14-2007

Re: how to make the synthesizer work with a clock

You should have similar lines for all clocks actually used in the design.  Note that you only get a "default period analysis" for clocks that have paths internal to the FPGA going from one flip-flop's Q, possibly though logic, to another flip-flop's D.  Otherwise there is no "period" that relates to a path that can be checked for timing.

-- Gabor
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Visitor milan.km
Visitor
8,772 Views
Registered: ‎11-12-2015

Re: how to make the synthesizer work with a clock

I have one clk=20 ns that go through all design ,but in one part i want 4 times of my clock,because of that i made another port and clk4x and made it 1.25 ns.

now when I want to synthesize it I dont have synthesize report for cllk just for clk4x

 

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Instructor
Instructor
8,769 Views
Registered: ‎08-14-2007

Re: how to make the synthesizer work with a clock

Without looking at the design, it's hard to say why, but most likely you don't have any flops clocked by the 20 ns clock whose output is used by other flops on that clock.  Without such a path, you won't see a period analysis.  You can open the RTL schematic to see if the original 20 ns clock is still in the design, and if so what it actually clocks.

-- Gabor
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Moderator
Moderator
8,759 Views
Registered: ‎07-01-2015

Re: how to make the synthesizer work with a clock

Hi @milan.km,

 

Please attach your code and constraints file here.

You are dividing the frequency or multiplying?

 

Thanks,
Arpan

Thanks,
Arpan
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Explorer
Explorer
8,747 Views
Registered: ‎04-28-2015

Re: how to make the synthesizer work with a clock

Hi @milan.km

 

Just as a check, do ensure you have written proper clock period constraints.
You can find information regarding all the constraints in http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf

Please share the constraint file along with the relevant code as requested above.

Regards,
Tushar.


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Moderator
Moderator
8,728 Views
Registered: ‎01-16-2013

Re: how to make the synthesizer work with a clock

Hi,

 

Why you are trying to use FPGA fabric to generate clocks?

This is not recommended practice to generate the clock. You can use DCM/PLL/MMCM (clock modulation blocks) to achive the functionality.

 

Which Device you are targetting?

 

Thanks,
Yash

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Visitor milan.km
Visitor
8,720 Views
Registered: ‎11-12-2015

Re: how to make the synthesizer work with a clock

this is the main code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity full is
port(p_1,p_2,p_3,p_4 : in unsigned(7 downto 0);
clk : in std_logic;
clk2x : in std_logic;
clk4x : in std_logic;
p_out : out unsigned(7 downto 0));
end full;
architecture full_arch of full is
component main is
port(pxin : in unsigned(7 downto 0);
clk : in std_logic;
clk2x : in std_logic;
clk4x : in std_logic;
pxo : out unsigned(7 downto 0));
end component;
component reg is
port(p1,p2,p3,p4 : in unsigned(7 downto 0);
     clk : in std_logic;
	  mo : out unsigned(7 downto 0));
end component;
signal po_int : unsigned(7 downto 0) := "00000000";
begin
f1 : component reg
     port map (p1 => p_1, p2 => p_2, p3 => p_3, p4 => p_4 , clk => clk, mo => po_int); 
f2 : component main
     port map (pxin => po_int, clk => clk , clk2x => clk2x , clk4x => clk4x , pxo => p_out);
end full_arch;

clk= 20 ns,clk2x=5 ns,clk4x=1.25 ns.

for the main code :
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.211ns (frequency: 191.902MHz)
  Total number of paths / destination ports: 48474 / 7198
-------------------------------------------------------------------------
Delay:               5.211ns (Levels of Logic = 8)
  Source:            f1/c1/r3/j_2 (FF)
  Destination:       f1/c1/r3/t3_7 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising
----------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk2x'
  Clock period: 3.758ns (frequency: 266.099MHz)
  Total number of paths / destination ports: 484 / 122
-------------------------------------------------------------------------
Delay:               3.758ns (Levels of Logic = 3)
  Source:            f2/d1/ena1 (FF)
  Destination:       f2/d1/ena3 (FF)
  Source Clock:      clk2x rising
  Destination Clock: clk2x rising
------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk4x'
  Clock period: 4.203ns (frequency: 237.925MHz)
  Total number of paths / destination ports: 2806 / 385
-------------------------------------------------------------------------
Delay:               4.203ns (Levels of Logic = 4)
  Source:            f2/d2/ad1_7 (FF)
  Destination:       f2/d2/Mram_buff1 (RAM)
  Source Clock:      clk4x rising
  Destination Clock: clk4x rising
-----------------------------------------------------
--------------------------this is for "reg" component---------------------
Speed Grade: -1

   Minimum period: 5.211ns (Maximum Frequency: 191.902MHz)
   Minimum input arrival time before clock: 1.567ns
   Maximum output required time after clock: 6.942ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.211ns (frequency: 191.902MHz)
  Total number of paths / destination ports: 48474 / 7198
--------------------------------------------this is for "main" component ----------------
Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 3.530ns (Maximum Frequency: 283.286MHz)
   Minimum input arrival time before clock: 1.159ns
   Maximum output required time after clock: 3.259ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk4x'
  Clock period: 3.530ns (frequency: 283.286MHz)
  Total number of paths / destination ports: 2800 / 321
-------------------------------------------------------------------------
Delay:               3.530ns (Levels of Logic = 3)
  Source:            d2/ad1_4 (FF)
  Destination:       d2/Mram_buff1 (RAM)
  Source Clock:      clk4x rising
  Destination Clock: clk4x rising

  Data Path: d2/ad1_4 to d2/Mram_buff1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              10   0.471   1.022  d2/ad1_4 (d2/ad1_4)
     LUT5:I0->O            4   0.094   0.496  d2/ad1_mux0001<5>11 (d2/N9)
     LUT5:I4->O            1   0.094   0.576  d2/ad1_mux0001<9>_SW0 (N36)
     LUT6:I4->O            1   0.094   0.336  d2/ad1_mux0001<9> (d2/ad1_mux0001<9>)
     RAMB18:ADDRB12            0.347          d2/Mram_buff1
    ----------------------------------------
    Total                      3.530ns (1.100ns logic, 2.430ns route)
                                       (31.2% logic, 68.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk2x'
  Clock period: 2.954ns (frequency: 338.524MHz)
  Total number of paths / destination ports: 505 / 80
-------------------------------------------------------------------------
Delay:               2.954ns (Levels of Logic = 3)
  Source:            d1/adr3_0 (FF)
  Destination:       d1/adr3_9 (FF)
  Source Clock:      clk2x rising
  Destination Clock: clk2x rising

  Data Path: d1/adr3_0 to d1/adr3_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               4   0.471   1.085  d1/adr3_0 (d1/adr3_0)
     LUT6:I0->O            1   0.094   0.480  d1/ena1_not00011_SW0_SW0 (N38)
     LUT6:I5->O           12   0.094   0.636  d1/ena1_not00011 (d1/adr3_and0000)
     LUT4:I2->O            1   0.094   0.000  d1/adr3_9_rstpot (d1/adr3_9_rstpot)
     FD:D                     -0.018          d1/adr3_9
    ----------------------------------------
    Total                      2.954ns (0.753ns logic, 2.201ns route)
                                       (25.5% logic, 74.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk2x'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              1.159ns (Levels of Logic = 1)
  Source:            pxin<7> (PAD)
  Destination:       d1/pi3_7 (FF)
  Destination Clock: clk2x rising

  Data Path: pxin<7> to d1/pi3_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.818   0.341  pxin_7_IBUF (pxin_7_IBUF)
     FDE:D                    -0.018          d1/pi1_7
    ----------------------------------------
    Total                      1.159ns (0.818ns logic, 0.341ns route)
                                       (70.6% logic, 29.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk4x'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              3.259ns (Levels of Logic = 1)
  Source:            d2/m/pou_7 (FF)
  Destination:       pxo<7> (PAD)
  Source Clock:      clk4x rising

  Data Path: d2/m/pou_7 to pxo<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDS:C->Q              1   0.471   0.336  d2/m/pou_7 (d2/m/pou_7)
     OBUF:I->O                 2.452          pxo_7_OBUF (pxo<7>)
    ----------------------------------------
    Total                      3.259ns (2.923ns logic, 0.336ns route)
                                       (89.7% logic, 10.3% route)

=========================================================================

I also cant understand why the clk frequency for the main code and for the reg conponent is the same.what about the main conponent?

21.PNG

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Moderator
Moderator
8,700 Views
Registered: ‎07-01-2015

Re: how to make the synthesizer work with a clock

Hi @milan.km,

 

Have you applied any timing constraints on the clock signals?

Please share the code for reg and main.

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor milan.km
Visitor
8,691 Views
Registered: ‎11-12-2015

Re: how to make the synthesizer work with a clock

no I didnt put any constraints.and I dont know how to do it.

reg

---------------- reg & add
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
------------------
entity reg is
port(p1,p2,p3,p4 : in unsigned(7 downto 0);
     clk : in std_logic;
	  mo : out unsigned(7 downto 0));
end reg;
------------------------------
architecture reg_syn of reg is
component corereg is
    Port ( pr : in  unsigned (7 downto 0);
           pi : in  unsigned (7 downto 0);
           clk : in  STD_LOGIC;
           pmi : out  unsigned (7 downto 0));
end component;
signal m1,m2,m3 : unsigned(7 downto 0) := (others => '0');
signal int_m : unsigned(9 downto 0) := (others => '0');
component ram2 is
port (Clk : in std_logic;
        --address : in integer range 0 to 4095;
        we : in std_logic;
        di : in unsigned(7 downto 0);
        do : out unsigned(7 downto 0));
end component;
signal po : unsigned(7 downto 0) := "00000000";
signal wre : std_logic := '0';
begin
 c1 : component corereg
      port map(pr => p1, pi => p2, clk => clk,pmi => m1 );  --ref image
 c2 : component corereg
      port map(pr => p1, pi => p3, clk => clk,pmi => m2 );  --pic1
 c3 : component corereg
      port map(pr => p1, pi => p4, clk => clk,pmi => m3 );  --pic2
 c4 : component ram2
      port map(clk => clk, we => wre, di => p1, do => po );
		process(clk,m1,m2,m3)
		variable sum_p : unsigned(9 downto 0) := "0000000000";
		begin
		sum_p := "00"&po + m1 + m2 + m3;
		mo <= sum_p(9 downto 2);
		end process;
		end reg_syn;

main

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity main is
port(pxin : in unsigned(7 downto 0);
clk : in std_logic;
clk2x : in std_logic;
clk4x : in std_logic;
pxo : out unsigned(7 downto 0));
end main;

architecture Behavioral of main is
component interpol1 is
port(clk : in std_logic;
     clk2x : in std_logic;
	  clk4x : in std_logic;
     pin : in unsigned(7 downto 0);
	  pout: out unsigned(7 downto 0));
end component;
component mean2 is
port( pi  : in unsigned(7 downto 0);
      clk : in std_logic;
		po : out unsigned(7 downto 0));
		--p1,p2,p3,p4,p5,p6,p7,p8,p9  : buffer signed(7 downto 0));
end component;
signal po_int : unsigned(7 downto 0) := "00000000";
begin
d1 : component interpol1
     port map (clk => clk, clk2x=> clk2x, clk4x => clk4x,pin => pxin,pout => po_int);
d2 : component mean2
	  port map (clk => clk4x, pi => po_int , po => pxo);

end Behavioral;
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Moderator
Moderator
8,332 Views
Registered: ‎07-01-2015

Re: how to make the synthesizer work with a clock

Hi @milan.km,

 

We have to put constraints to make the tool understand our timing requirements.

For constraining the clock follow the following steps:

1.Go to Tools->Constraints editor in ISE project navigator.(snapshot-1)

2.Click on the unconstrained clock say "clk".(snapshot-2)

3. Give the clock period in the time (snapshot-3)

4.Save the changes(snapshot-4)

5.Click on design and go through .ucf file to see the constraints(snapshot-4 and 5)

6.Run implementation and then see the static timing report.

 

Please go through the following video. Hope it will be helpful to you.

https://www.youtube.com/watch?v=KF4EVN93EFI

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor milan.km
Visitor
8,326 Views
Registered: ‎11-12-2015

Re: how to make the synthesizer work with a clock

thanks @arpansur.it was so help ful.

can u help me with "why the main code and the reg component have the same frequency"?

I checked them all,they work properly.but I dont know ehy the clks are the same,what about the main component it should make the critical path longer and decrease the frequency.

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Visitor milan.km
Visitor
8,314 Views
Registered: ‎11-12-2015

Re: how to make the synthesizer work with a clock

dear @arpansur

I also wanted to ask if I have more than one clk as u see in my code.

clk=20

clk2x=5

clk4x=1.25

and I want to have a report of clock of sysyem which one should be selected?

I mean which one is logical?

and the maximum freq based on each of clks(clk,clk2x,xlk4x) is diffrent?

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Moderator
Moderator
8,312 Views
Registered: ‎07-01-2015

Re: how to make the synthesizer work with a clock

Hi @milan.km,

 

Have you applied the constraints?

Is it showing same frequency after constraint is applied to it?

 

Is it you are talking about net delay?

If so please don't be confused between net delay and clock period.

 

Thanks,
Arpan

Thanks,
Arpan
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Moderator
Moderator
8,307 Views
Registered: ‎07-01-2015

Re: how to make the synthesizer work with a clock

Hi @milan.km,

 

If you are constraining all the clocks then all are reported in timing report.

Is it your concern?(correct me if I am wrong)

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor milan.km
Visitor
8,299 Views
Registered: ‎11-12-2015

Re: how to make the synthesizer work with a clock

yes they are the same.

and when I did this for the main component and I SELECT clk as my constraint,I just have report for clk2x and clk4x and not for clk

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Visitor milan.km
Visitor
8,297 Views
Registered: ‎11-12-2015

Re: how to make the synthesizer work with a clock

I want to get ris of problems of working with multiple clks, do u think that would be ok to put clk4x as my input.

and make clk2x and clk by clk deviding,

do u think thats a goot idea??? because I think working with multiple clks have some problems

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Moderator
Moderator
8,293 Views
Registered: ‎07-01-2015

Re: how to make the synthesizer work with a clock

Hi @milan.km,

 

Yes you can go with a single clock and generate multiple clocks out of it.

 

If you want to go for frquency divider a simple counter will help and if you want to go for freuency multiplier then DCM/PLL will be helpful.

 

Thanks,
Arpan

Thanks,
Arpan
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