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Visitor kimonides
Visitor
8,434 Views
Registered: ‎03-01-2016

ieee is not declared/std_logic_vector is not declared error

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Hello I was writing a code for a look ahead adder but I keep getting this error when I Check Syntax.

If someone could help me I would be really thankful.

Here is the code:

 

library ieee;
use IEEE.STD_LOGIC_1164.all;



entity Look_Ahead_Adder is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           CIN : in  STD_LOGIC;
           S : out  STD_LOGIC_VECTOR (3 downto 0);
           COUT : out  STD_LOGIC);
end Look_Ahead_Adder;
---------------------------------------------------------------------------------------------------------------------






architecture Behavioral of Look_Ahead_Adder is

signal P: STD_LOGIC_VECTOR(3 downto 0);
signal G: STD_LOGIC_VECTOR(3 downto 0);
signal C: STD_LOGIC_VECTOR(2 downto 0);

---------------------------------------------------------------------------------------------------------------------

component Carry_Generate_Propagate_Unit is 
	Port (  A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           P : out  STD_LOGIC_VECTOR (3 downto 0);
           G : out  STD_LOGIC_VECTOR (3 downto 0));
end component Carry_Generate_Propagate_Unit;



component Carry_Look_Ahead_Unit is
    Port ( G : in  STD_LOGIC_VECTOR (3 downto 0);
           P : in  STD_LOGIC_VECTOR (3 downto 0);
           CIN : in  STD_LOGIC;
           C : out  STD_LOGIC_VECTOR (3 downto 0));
end component Carry_Look_Ahead_Unit;



component Sum_Unit is
    Port ( P : in  STD_LOGIC_VECTOR (3 downto 0);
           C : in  STD_LOGIC_VECTOR (2 downto 0);
           CIN : in  STD_LOGIC;
           S : out  STD_LOGIC_VECTOR (3 downto 0));
end component Sum_Unit;
----------------------------------------------------------------


begin


	CGPU: Carry_Generate_Propagate_Unit port map ( A=>A , B=>B , P=>P , G=>G );

	CLAD: Carry_Look_Ahead_Unit port map ( G=>G , P=>P , CIN=>CIN , C=>C );

	SU: Sum_Unit port map ( P=>P , C=>C , CIN=>CIN , S=>S );



end Behavioral;
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Xilinx Employee
Xilinx Employee
16,009 Views
Registered: ‎05-20-2015

Re: ieee is not declared/std_logic_vector is not declared error

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Hi @kimonides,

The port C (3 downto 0) of Carry Look Ahead Unit is portmapped to signal C (2 downto 0).

Can you please correct that and check?

 

-Rajesh

3 Replies
Moderator
Moderator
8,424 Views
Registered: ‎06-24-2015

Re: ieee is not declared/std_logic_vector is not declared error

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Hi @kimonides,

 

Please post the files CGPU, CLAD and SU here as well.

Thanks,
Nupur
--------------------------------------------------------------------------------------------
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Highlighted
Xilinx Employee
Xilinx Employee
16,010 Views
Registered: ‎05-20-2015

Re: ieee is not declared/std_logic_vector is not declared error

Jump to solution

Hi @kimonides,

The port C (3 downto 0) of Carry Look Ahead Unit is portmapped to signal C (2 downto 0).

Can you please correct that and check?

 

-Rajesh

Visitor kimonides
Visitor
8,417 Views
Registered: ‎03-01-2016

Re: ieee is not declared/std_logic_vector is not declared error

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Thank you very much I found the mistake it was in the Carry Look Ahead Unit with the vector size.

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