02-14-2017 07:10 PM
There's no "nice" way to do it. The math_real library isn't supported because those floating-point operations are hard - and often not practical to run in a combinational way.
Vivado does include the Floating Point IP core, which can do the required maths. However, it'll require a lot of cycles to run and interfacing is not trivial (you can't just use "+" anywhere in your code, you actually have to send the operands and the operation off to the IP core to be added).
02-14-2017 07:18 PM
@u4223374 Thank you for the reply.
Actually, what i want is to add a function to calculate the bit width of the bus which is not required to be synthesized into logic. In this function, ceil and log2 function inside ieee.math_real are used. Is there an alternative for ceil and log2?
function f_Bits(nr : integer) return natural is variable v_i : integer; begin if nr < 2 then v_i := 1; else v_i := integer(ceil(log2(real(nr)))); end if; return v_i; end f_Bits;
02-14-2017 08:16 PM
02-15-2017 05:23 AM - edited 02-15-2017 05:24 AM
@softwind555 "ceil and log2 function inside ieee.math_real are used. "
Vivado synthesis DOES support math_real for elaboration-time static calculations such as bit width. See this thread for documentation links:
I've been asking Xilinx to fix that badly outdated AR52304 since 2013, e.g. :
How many years and requests does it take to get Xilinx to fix bad documentation that continues to confuse both Xilinx users and synthesis forum moderators?
02-15-2017 06:19 PM
@brimdavis Thanks a lot for your input.
But, It's found it's still not supported in the latest Vivado 2016.4. I can still get error report. See picture below for error info.
02-16-2017 05:17 AM
@softwind555 "But, It's found it's still not supported in the latest Vivado 2016.4."
It is supported by the synthesizer- have you actually tried running synthesis and looking at the synthesis report?
All you should need is a use ieee.math_real.all at the top of your file.
"See picture below for error info."
Xilinx's buggy syntax checker within the editor is best turned off, as it reports bogus errors like this for legal VHDL constructs.
04-18-2018 12:49 AM
what does this AR acutally mean?
does it mean the math_real functions cannot be synthesized to hardware? Because they do work fine in testbenches. Of course they cannot be simply synthesized to hardware, but the AR is unclear to me.