We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

## Synthesis

Showing results for
Do you mean

Solved
Explorer
Posts: 145
Registered: ‎05-14-2015

Hello, it is noticed that IEEE library "math_real" is not supported in Vivado. Is there an alternative way for it?

Accepted Solutions
Scholar
Posts: 2,846
Registered: ‎04-26-2015

## Re: ieee.math_real support with Vivado

The suggestion here is to write your own log2 function; it doesn't have to be efficient because it'll never be implemented. That seems like a reasonable approach.

All Replies
Scholar
Posts: 2,846
Registered: ‎04-26-2015

## Re: ieee.math_real support with Vivado

There's no "nice" way to do it. The math_real library isn't supported because those floating-point operations are hard - and often not practical to run in a combinational way.

Vivado does include the Floating Point IP core, which can do the required maths. However, it'll require a lot of cycles to run and interfacing is not trivial (you can't just use "+" anywhere in your code, you actually have to send the operands and the operation off to the IP core to be added).

Explorer
Posts: 145
Registered: ‎05-14-2015

## Re: ieee.math_real support with Vivado

@u4223374 Thank you for the reply.

Actually, what i want is to add a function to calculate the bit width of the bus which is not required to be synthesized into logic. In this function, ceil and log2 function inside ieee.math_real are used. Is there an alternative for ceil and log2?

```function f_Bits(nr : integer) return natural is
variable v_i : integer;
begin
if nr < 2 then
v_i := 1;
else
v_i := integer(ceil(log2(real(nr))));
end if;
return v_i;
end f_Bits;```
Scholar
Posts: 2,846
Registered: ‎04-26-2015

## Re: ieee.math_real support with Vivado

The suggestion here is to write your own log2 function; it doesn't have to be efficient because it'll never be implemented. That seems like a reasonable approach.

Xilinx Employee
Posts: 5,894
Registered: ‎08-01-2008

## Re: ieee.math_real support with Vivado

Currently, the Vivado Synthesis tool does not support IEEE MATH_REAL and IEEE PROPOSED package libraries.

This was published in this ARs
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Highlighted
Voyager
Posts: 292
Registered: ‎04-26-2012

## Re: ieee.math_real support with Vivado

[ Edited ]

@softwind555 "ceil and log2 function inside ieee.math_real are used. "

Vivado synthesis DOES support math_real for elaboration-time static calculations such as bit width. See this thread for documentation links:

@balkris @achutha "Currently, the Vivado Synthesis tool does not support IEEE MATH_REAL and IEEE PROPOSED package libraries. <snip> https://www.xilinx.com/support/answers/52304.html"

I've been asking Xilinx to fix that badly outdated AR52304 since 2013, e.g. :

How many years and requests does it take to get Xilinx to fix bad documentation that continues to confuse both Xilinx users and synthesis forum moderators?

-Brian

Explorer
Posts: 145
Registered: ‎05-14-2015

## Re: ieee.math_real support with Vivado

@brimdavis Thanks a lot for your input.

But, It's found it's still not supported in the latest Vivado 2016.4. I can still get error report. See picture below for error info.

Voyager
Posts: 292
Registered: ‎04-26-2012

## Re: ieee.math_real support with Vivado

@softwind555 "But, It's found it's still not supported in the latest Vivado 2016.4."

It is supported by the synthesizer- have you actually tried running synthesis and looking at the synthesis report?

All you should need is a use ieee.math_real.all at the top of your file.

"See picture below for error info."

Xilinx's buggy syntax checker within the editor is best turned off, as it reports bogus errors like this for legal VHDL constructs.

-Brian

Explorer
Posts: 145
Registered: ‎05-14-2015

## Re: ieee.math_real support with Vivado

@brimdavis, Thanks a lot! Indeed, synthesis doesn't report any error for this.
Scholar
Posts: 1,344
Registered: ‎10-10-2014

## Re: ieee.math_real support with Vivado

what does this AR acutally mean?

"AR# 52304 Does Vivado Synthesis support IEEE MATH_REAL and PROPOSED package libraries?"

does it mean the math_real functions cannot be synthesized to hardware? Because they do work fine in testbenches. Of course they cannot be simply synthesized to hardware, but the AR is unclear to me.