07-26-2021 12:59 PM
I've inherited a messy ISE 10.3 Spartan 3 project that has some strange VHDL coding constructs. In one example, they're creating a std_logic signal and assigning a constant 'Z', but then using the signal in "if/then" type of logic statements comparing to the value of '1' and '0'. It's not being used as a top level bi-directional port, or even an internal bi-directional bus, but simply an internal signal that's always 'Z'.
What would this signal implement as inside the FPGA? a constant '1' or '0'?
07-26-2021 01:10 PM
If you can implement the design, open it up and look and see. I would guess a '0'. I wouldn't be surprised if you'd be able to find a synthesis and/or implementation message related to the signal. If the signal is just used in an if statement, that's interesting. A 'Z' doesn't equal a '1' or a '0', but hard to say for sure that's what would happen in synthesis. Again, I'd search down the relevant signal in the open implementation's netlist, and hit F4 to open the schematic and you can see how it got implemented.
07-27-2021 12:33 AM
If it is as you suggest, then the logic will likely be simplified to whatever the else case is.Maybe it was an internal tri-state at some point. Are you sure the signal doesnt have multiple drivers?
If you post the code, maybe we could provide more insight?