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inout from block giving weird error in synthesis

Explorer
Posts: 146
Registered: ‎07-29-2009

inout from block giving weird error in synthesis

I am trying to convert the internal four-wire SPI to three-wire.  I have inferred a single inout, but Vivado is giving a weird critical warning for what is “simple” code in synthesis. I have an internal block in the block design where I made the inout an external port, as you can see in this picture:

spi_sdio.PNG

 

This is the critical error.  It should be noted that I'm programming in Verilog.

 

Designutils 20-1595] In entity reference_emitter_spidemux_0_0, 
connectivity of net SPI_SDIO cannot be represented in VHDL.
 VHDL lacks syntax to connect the following inout terminals to a differently-named net:  
  inout SPI_SDIO Resolution:
 Check whether terminals really need inout direction and substitute input or output as needed.
 It may also be possible to rename the net to match the terminal.

 

Here’s the code snippet of what's in the spidemux_0 block:

    inout wire SPI_SDIO,

    output wire SPI_CLK,

    output reg [3:0] SPI_SS

 

 

    assign SPI_SDIO = reallyread ? 1'bz : spi_MOSI_i;

    assign spi_MISO_o = SPI_SDIO;

 

Any thoughts on where this message is coming from?  I went ahead and implemented where, I think, the message is not propagated.  I'd prefer to NOT have a synthesis error though.  I am using the designutils library in the TCL store to wrap the code for a testbench.

 

Teacher
Posts: 5,146
Registered: ‎03-31-2012

Re: inout from block giving weird error in synthesis

@petersk i think your block diagram wrapper is coming out in vhdl and it seems you can't propagate a verilog inout through vhdl ports. Can you change your implementation language to verilog (assuming it's set to vhdl now) and see if a wrapper in verilog allows this?

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Explorer
Posts: 146
Registered: ‎07-29-2009

Re: inout from block giving weird error in synthesis

I think my implementation language is set to Verilog.  At least the "target language" is in the "Project Settings" : General. Is there somewhere else I could set it? In the Sim it's set to mixed.  I think it might have to do with the designutils setting?

I'm using the -Verilog switch in the call though:

create_spidemux.tcl:::xilinx::designutils::write_ip_integrator_testbench -verilog -output $myhome/spi_demux/spi_demux.srcs/spidemux_tb.v -addToProject

 

Highlighted
Explorer
Posts: 209
Registered: ‎04-26-2012

Re: inout from block giving weird error in synthesis

@petersk "I have inferred a single inout, but Vivado is giving a weird critical warning for what is “simple” code in synthesis."

 

If you're using 2016.4, IPI Block Diagrams now default to Out-of-Context generation, which can cause problems with internal tristates of an inferred nature.

 

Try setting the Generate Block Design synthesis option to "Global" instead of "Out-Of-Context"

 

See this thread for discussion of inferred tristates in BD IP :

https://forums.xilinx.com/t5/Implementation/tristate-logic-not-implemented-in-2016-4/m-p/742355

 

Although not exactly the same error, your odd error message might be related to how the tool internally attempts to wire up a bidirectional signal that's down a ways in the BD hierarchy.

 

-Brian

Explorer
Posts: 146
Registered: ‎07-29-2009

Re: inout from block giving weird error in synthesis

I can't seem to find out how to make it NOT do the IP in out of context. Can you point me in the right direction?

Kurt

Explorer
Posts: 209
Registered: ‎04-26-2012

Re: inout from block giving weird error in synthesis

@petersk "I can't seem to find out how to make it NOT do the IP in out of context. Can you point me in the right direction?"

 

See picture below; hit the "generate" button after changing the setting to global, then re-run synthesis:

 

ipi_settings.png

 

-Brian