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mad.sky
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Registered: ‎01-15-2015

inserting compile date into Verilog or VHDL code automatically

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Hello,

I would like to have a register in firmware that reports that firmware's compile date. The register's contents should be rewritten automatically every time the firmware is compiled.

I am having troubles figuring out how to do that using ISE 14.7 (on Windows). One way is to use TCL script or "make" utility for compilation, but I would like to keep using ISE Project Manager since it's so much more convenient.

The bulk of my source code is in Verilog, but if VHDL is required for this to work, that's not a problem. I can always isolate that piece into a separate VHDL file.

thanks.

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dwisehart
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Registered: ‎06-23-2013
With Vivado, we add this to the constraints file:

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Inside the Verilog we instantiate the USR_ACCESSE2 component:

wire [31:0] wBuild;
USR_ACCESSE2 mUsrAccess
(
.DATA ( wBuild ),
.CFGCLK (),
.DATAVALID ()
);

USR_ACCESS has been around since at least Virtex-4. It should be accessible from ISE as well.

Daniel

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avrumw
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Registered: ‎01-23-2009

In the project navigator (ise) GUI, I don't think there is any way to do this automatically.

 

Using scripts (batch or Tcl), it is quite easy to do.

 

Furthermore, in Vivado and even PlanAhead, I am pretty sure that it can be done with the pre_synth hook scripts, but I don't think you can do it in projNav.

 

Avrum

 

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dwisehart
Scholar
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20,923 Views
Registered: ‎06-23-2013
With Vivado, we add this to the constraints file:

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Inside the Verilog we instantiate the USR_ACCESSE2 component:

wire [31:0] wBuild;
USR_ACCESSE2 mUsrAccess
(
.DATA ( wBuild ),
.CFGCLK (),
.DATAVALID ()
);

USR_ACCESS has been around since at least Virtex-4. It should be accessible from ISE as well.

Daniel

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gszakacs
Instructor
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Registered: ‎08-14-2007

That's cool.  I don't see USR_ACCESS in Spartan6, though.

 

This topic seems to come up quite frequently, and it always seemed to me that it is a deficiency in Verilog and VHDL not to have date stamping built into the language.  For my designs I typically have a version register, which I often forget to update and end up running through a build twice.

 

Of course the date and time are in the .bit file header.  But you don't have access to that inside the FPGA.  We have some systems where there's a small microcomputer that stores the .bit files and programs the FPGA.  Then that micro can tell you when the file was built because it stores the whole file with header.  The header gets stripped from the .bit file when you generate a PROM file, so even with JTAG you'd have to compare the bitstream itself to tell if you had the right version, and if you didn't still have the matching bitstream file you couldn't determine the date.

-- Gabor
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mad.sky
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Registered: ‎01-15-2015

Thanks dwisehart,

using USR_ACCESSE2 keyword, found this appnote:

http://www.xilinx.com/support/documentation/application_notes/xapp497_usr_access.pdf

 

Turns out that Project Navigator also supports that, the option is located in Generate Programming File properties dialog, Configuration Options tab:

-g USR_ACCESS should be set to TIMESTAMP.

Thanks for your help.

traianm
Observer
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Registered: ‎06-22-2017

Has there been a resolve to this issue?

 

The original question was how to use TIMESTAMP in SPARTAN 6

 

All the answers seem to be pointing to XAPP497 which deals on ho wto use TIMESTAMP in ISE, but not in SPARTAN 6

 

The -g USR_ACCESS is not available in ISE for SPARTAN 6 devices.

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