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Adventurer
Adventurer
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Registered: ‎07-09-2014

is it wrong to define multiple architecture in VHDL entity?

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Hi all,

In VHDL, one can define two architectures inside an entity in a file. There was a post about it but using multiple architectures in different files here:

https://forums.xilinx.com/t5/Design-Methodologies-and/Entity-and-Architecture-in-different-files/m-p/806402#M4401

@drjohnsmith  or @drjohnsmith2 

said it is an ASIC practice, dont do it in FPGAs, just one architecture body and one entity in one file but did not mention about why it is not a good practice to use multiple architectures in one entity in one file.

I think in coding style it seems compact. 

Any comment about it?

Regards,

Burak

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: is it wrong to define multiple architecture in VHDL entity?

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In general, people do not use multiple architectures. They will use generics to specify design function in a single architecture. (this is what I have always done and Ive never worked with any engineers that use multiple architectures)

Your example shows multiple architectures using generates + direct instantiation to specify the architecture. This would definitely be the prefered way as it appears pretty obvious what is going on. This has been possible since VHDL 1993. The other way to do it would be via configurations (from VHDL 1987) which are really annoying and I rarely see used anywhere.

Usually, I think most designers would just create separate entites for each setup. (LDPC_ENABLE and LDPC_DISABLE). That is what designers are used to.

I dont think its a tool problem, just and engineer understanding problem. You will get resistance because it is not the preferred way of working.

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Scholar
Scholar
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Registered: ‎08-07-2014

Re: is it wrong to define multiple architecture in VHDL entity?

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@bbinb,

It is not a standard practice with FPGA designs.

I also do not know if the synthesis tools can handle a multi-arch VHDL entities. I never do it.

I also think that a multi-arch entity leads to code cluttering. Keep it clean, keep it separate for others to understand your RTL better.

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: is it wrong to define multiple architecture in VHDL entity?

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When VHDL was invented in the 1980's, things were very different, Just think, no mobile phones, C++ had not been invented, teletypes were normal !

Dont propagate an old technique in VHDL any more than you would use say BASIC code in your project ..

What your aiming to doing is making the code redable, not compact, Hunting in many files for entities is hard enough with the file name and the entity the same, and then one architecture in each file.

Keep one entity and one architecture in each file,
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Adventurer
Adventurer
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Registered: ‎07-09-2014

Re: is it wrong to define multiple architecture in VHDL entity?

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@drjohnsmith 

@dpaul24 

Thanks for the comments,

Let me give an example code:

entity PCM_INTERFACE is
GENERIC (
M : integer := 50 ;
N : integer := 100 ;
M_BIT : integer := 6 ; --log2(M)
N_BIT : integer := 7 ; --log2(N)
CLK_FREQ : integer := 80000000
);
PORT (
CLK : IN STD_LOGIC;
DOUT_VALID : IN STD_LOGIC ;
DATA_REQUEST: OUT STD_LOGIC := '0';
DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
PCM_DATA : OUT STD_LOGIC := '0' ;
PCM_CLK : OUT STD_LOGIC := '0'
);
end PCM_INTERFACE;

This module has two architecture:

architecture LDPC_DISABLE of PCM_INTERFACE is

and

architecture LDPC_ENABLE of PCM_INTERFACE is

It is instantiated in top level as:

entity TOP_MODULE is
generic (
M : integer := 50 ;
N : integer := 128 ;
M_BIT : integer := 6 ; --log2(M)
N_BIT : integer := 7 ; --log2(N)
MESAGE_NUMBER : integer := 21 ;
CLK_FREQ : integer := 6400000 ;
PULSE_FREQ : integer := 1000000 ;
imp_type : string:="LDPC_ENABLE" -- LDPC_ENABLE or LDPC_DISABLE
);
port (...)

...

begin

...

G1: if imp_type="LDPC_DISABLE" generate
U1: entity work.PCM_INTERFACE(LDPC_DISABLE)
GENERIC MAP(
M => M ,
N => N ,
M_BIT => M_BIT , --log2(M)
N_BIT => N_BIT , --log2(N)
CLK_FREQ => CLK_FREQ
)
PORT MAP(
CLK => CLK ,
DOUT_VALID => PCM_DOUT_VALID ,
DATA_REQUEST=> PCM_DATA_REQUEST,
DATA_IN => PCM_DOUT,
PCM_DATA => PCM_DATA ,
PCM_CLK => PCM_CLK);
end generate;

G2: if imp_type="LDPC_ENABLE" generate
U2: entity work.PCM_INTERFACE(LDPC_ENABLE)
GENERIC MAP(
M => M ,
N => N ,
M_BIT => M_BIT , --log2(M)
N_BIT => N_BIT , --log2(N)
CLK_FREQ => CLK_FREQ)
PORT MAP(
CLK => CLK ,
DOUT_VALID => PCM_DOUT_VALID ,
DATA_REQUEST=> PCM_DATA_REQUEST,
DATA_IN => PCM_DOUT,
PCM_DATA => PCM_DATA ,
PCM_CLK => PCM_CLK);
end generate;

In TOP module, by only changing generic parameter imp_type, the code is synthesized in one of both ways. It is not very easy to write one architecture and use generic constants from a package or generic field to do two different implementations one having LDPC encoding and other not have. 

This code is synthesized and implemented in ISE 14.1 on a Spartan 3 FPGA with no problem.

With all my respect, I still could not get the clue about the problem of using multiple architecture implementations for one entity in a file. By the way I wrote both architecture implementations in one file not seperate files. If I dont use multiple architectures then I need two files named like PCM_INTERFACE_LDPC_ON.vhd and PCM_INTERFACE_LDPC_OFF.vhd and comment one instantiation in top.vhd according to case. Also comment the component declerations possibly. 

Isn't it possible to accept this method okay and a different coding style whether some likes and some dont. Like records in VHDL. I never used record definitions but I saw an example code and I loved it. Instead of writing tons of lines in the file with record type it is more clear and compact.

Regards,

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Scholar
Scholar
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Registered: ‎08-01-2012

Re: is it wrong to define multiple architecture in VHDL entity?

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In general, people do not use multiple architectures. They will use generics to specify design function in a single architecture. (this is what I have always done and Ive never worked with any engineers that use multiple architectures)

Your example shows multiple architectures using generates + direct instantiation to specify the architecture. This would definitely be the prefered way as it appears pretty obvious what is going on. This has been possible since VHDL 1993. The other way to do it would be via configurations (from VHDL 1987) which are really annoying and I rarely see used anywhere.

Usually, I think most designers would just create separate entites for each setup. (LDPC_ENABLE and LDPC_DISABLE). That is what designers are used to.

I dont think its a tool problem, just and engineer understanding problem. You will get resistance because it is not the preferred way of working.

View solution in original post

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Adventurer
Adventurer
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Registered: ‎07-09-2014

Re: is it wrong to define multiple architecture in VHDL entity?

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@richardhead 

Thank you for the answer.

Your sentence "I dont think its a tool problem, just and engineer understanding problem. You will get resistance because it is not the preferred way of working." is the clearest answer for me.

I think, designers prefer not having multiple architecture in an entity because it is not the common practice. I also never used it this way, but I saw a colleague wrote a code with multiple architectures (the example above) and told him not to do so. He asked why and I could not find any reasonable answer. And still I cant say "because of this and that you should not use multiple architectures" as there is no harm in practice, but it is not very common, which also can be a reason not to use it, still cant force someone not to use multiple architecture in an entity.

Regards,

Burak

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