UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
248 Views
Registered: ‎06-18-2018

issue since 2018.3 using resize and sra in vhdl2008

Jump to solution

Hi,

after migrating vhdl2008 code using resize() and sra from 2017.4 to 2018.3 we find Vivado dropping to much logic.

We wrote a small code snippet to show the issue, please see files attached.

Change file properties to VHDL2008 to use test.vhd after importing.

Wrongness of result changes if changing order of if/then/elsif/... .

Target : XC7A50T,   OS : Windows 7/64  32G

Thanx & Brgds, Jens Michaelsen

(could not find similar looking issue in late postings, pls. excuse if I missed it)

Tags (1)
Comparison_of_results.jpg
0 Kudos
1 Solution

Accepted Solutions
Highlighted
187 Views
Registered: ‎06-18-2018

Re: issue since 2018.3 using resize and sra in vhdl2008

Jump to solution

All tools we used so far generate proper code, only new versions of vivado silently fail with varying results, a bit scary, Thanx for your hint.

0 Kudos
5 Replies
Scholar richardhead
Scholar
231 Views
Registered: ‎08-01-2012

Re: issue since 2018.3 using resize and sra in vhdl2008

Jump to solution

Is it actually not working? Or is 2018.3 just more efficient?

0 Kudos
228 Views
Registered: ‎06-18-2018

Re: issue since 2018.3 using resize and sra in vhdl2008

Jump to solution

The resulting 2018.3 netlist does not do what the code is intended to do, and did well before migration.

Vivado now "optimizes" out a bit too much to get a valid result. Did verify this with 2019.1 too, same wrong result.

0 Kudos
204 Views
Registered: ‎01-22-2015

Re: issue since 2018.3 using resize and sra in vhdl2008

Jump to solution

I understood that sra never worked properly and was dropped from the VHDL language - and replaced by shift_right.   Please see <this> thread for more information.

Mark

0 Kudos
Highlighted
188 Views
Registered: ‎06-18-2018

Re: issue since 2018.3 using resize and sra in vhdl2008

Jump to solution

All tools we used so far generate proper code, only new versions of vivado silently fail with varying results, a bit scary, Thanx for your hint.

0 Kudos
Scholar richardhead
Scholar
169 Views
Registered: ‎08-01-2012

Re: issue since 2018.3 using resize and sra in vhdl2008

Jump to solution

sra and srl were never dropped because they are reserved words and basic operators.

They never used to be defined for unsigned/signed types in numeric_std, there was shift_left and shift_right instead.

They were added for unsigned/signed in VHDL 2008.

So they havent gone away, and should work correctly!