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Registered: ‎06-18-2018

issue since 2018.3 using resize and sra in vhdl2008

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Hi,

after migrating vhdl2008 code using resize() and sra from 2017.4 to 2018.3 we find Vivado dropping to much logic.

We wrote a small code snippet to show the issue, please see files attached.

Change file properties to VHDL2008 to use test.vhd after importing.

Wrongness of result changes if changing order of if/then/elsif/... .

Target : XC7A50T,   OS : Windows 7/64  32G

Thanx & Brgds, Jens Michaelsen

(could not find similar looking issue in late postings, pls. excuse if I missed it)

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453 Views
Registered: ‎06-18-2018

All tools we used so far generate proper code, only new versions of vivado silently fail with varying results, a bit scary, Thanx for your hint.

View solution in original post

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Scholar
Scholar
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Registered: ‎08-01-2012

Is it actually not working? Or is 2018.3 just more efficient?

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Registered: ‎06-18-2018

The resulting 2018.3 netlist does not do what the code is intended to do, and did well before migration.

Vivado now "optimizes" out a bit too much to get a valid result. Did verify this with 2019.1 too, same wrong result.

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Registered: ‎01-22-2015

I understood that sra never worked properly and was dropped from the VHDL language - and replaced by shift_right.   Please see <this> thread for more information.

Mark

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Registered: ‎06-18-2018

All tools we used so far generate proper code, only new versions of vivado silently fail with varying results, a bit scary, Thanx for your hint.

View solution in original post

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Scholar
Scholar
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Registered: ‎08-01-2012

sra and srl were never dropped because they are reserved words and basic operators.

They never used to be defined for unsigned/signed types in numeric_std, there was shift_left and shift_right instead.

They were added for unsigned/signed in VHDL 2008.

So they havent gone away, and should work correctly!