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Voyager
Voyager
623 Views
Registered: ‎06-26-2015

keep module ??

how to keep module from synthesis out?

i tried this, but it give me syntax error

 

(*keep_hierarchy=*yes**) test_module(in1,in2,out1);

 

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Xilinx Employee
Xilinx Employee
593 Views
Registered: ‎05-22-2018

Hi @s002wjhw ,

Is your requirement is equivalent to what is shown below?

TopModule

           ----->      module 1

           ----->      module 2

           ----->      module 3

Do you want to synthesize all modules including TopModule except module3?

If that is the requirement, you can use TRANSLATE_OFF/TRANSLATE_ON.

Check page no. 60 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis.pdf

Thanks,

Raj

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Xilinx Employee
Xilinx Employee
585 Views
Registered: ‎05-14-2008

Just to correct your syntax error of the "keep_hierarchy" attribute.

(*keep_hierarchy="yes" *) test_module(in1,in2,out1);

Use "" instead of **.

Is your module missing after Synthesis?

Keep hierarchy is to just keep the hierarchy boundary of the module during Synthesis.

If for some reason this module is totally removed by Synthesis, keep hierarchy is not the one to resolve it.

Please elaborate what exactly the problem you have with this module.

-vivian

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Moderator
Moderator
574 Views
Registered: ‎11-04-2010

Hi, @s002wjhw ,

1. To keep the module boundary, you can use the dont_touch attribute.

Ex: (* dont_touch = "true" *) test_module(in1,in2,out1);

2. To avoid the module being removed, you should confrim the module has active input and the output of the module will be used on the FPGA ports eventually. 

   

 

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Voyager
Voyager
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Registered: ‎06-26-2015

hi the test module was optimized out(because its not connect to IO, only internal signal), its some test module i like to keep inside the FPGA.

top module

module1

test_module  <- i like to keep this one from synthesis out

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Moderator
Moderator
533 Views
Registered: ‎11-04-2010

Hi, @s002wjhw ,

In the design, you can try to connect the output of test module to ILA. This will keep the module.

If you just intend to know the utilization of the test module, you can also set the test mdoule as top then run synth&impl.

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Moderator
Moderator
515 Views
Registered: ‎07-21-2014

@s002wjhw 

In that case, the tool will remove the module as there are no inputs and outputs connected to the main design. 
What is the use of such a module in the design? 

I am not sure about the usage, but you can try a trick:

1. Synthesize the module as OOC/top and generate the netlist
2. Mark this module as black_box in the stub file
3. Mark the instantiation as dont_touch
4. Run Synthesis

This may allow you to complete synthesis, but the implementation(opt_design) phase may remove this module.

Thanks
Anusheel 

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