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Contributor
Contributor
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Registered: ‎07-26-2018

large shift register synthesis issue

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Hi, I try to synthesis very large shift register but after 1 hour it's still continue.

in the following code, r1,r2,r3 my shift register and  I defined "frame type" as follows.

subtype pixel8 is std_logic_vector(7 downto 0); 
type frame_type is array(natural range <>) of pixel8;

So, What can I do to r1, r2, r3 for rapid synthesis ?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;

entity workgroup is
    port (
        clk              : in  std_logic;
        Fcntrl_active_i  : in  std_logic;
        Fcntrl_rd_en_i   : in std_logic;
        conv_running_o   : out std_logic;
        din_w            : in  std_logic_vector(7 downto 0);
        dout_W           : out std_logic_vector(7 downto 0)
    );
end workgroup;

architecture rtl of workgroup is
        
   
    component convolution2d is
                    port (
                        clk      : in  std_logic;
                        start    : in  std_logic;
                        window   : in  frame9;
                        conv_running    : out std_logic;
                        pixel    : out std_logic_vector(7 downto 0)
                    );
    end component;


    signal r1, r2 : frame_type(0 to 1279) := (others => (others => 'Z'));
    signal r3: frame_type(0 to 1279) := (others => (others => 'Z'));
    signal running2 : std_logic:='0';
    signal cnt_col : natural := 0;
    signal col : integer:=1279;
    signal pixcounter : integer:=1;
    signal conv_window : frame9;
    
    attribute DONT_TOUCH : string;
    attribute DONT_TOUCH of r1,r2,r3: signal is "TRUE";
    
     type state_type is (st_idle, st_r3,st_r2, st_conv);
     signal  state : state_type := st_idle;
     
begin
    process(clk)
    begin
        if rising_edge(clk) then  
            running2<='0';
            if Fcntrl_active_i='1' then                                                                  
                case state is
                    when st_idle =>
                        if Fcntrl_rd_en_i='1' then
                            r1<= (others => (others => '0'));
                            pixcounter<=0;
                            state<=st_r2;
                        end if;   
                    when st_r2=>
                        r3<=r3(1 to 1279) & din_w;     
                        if pixcounter=1280 then
                            r2<=r3;
                            state<=st_r3;
                            pixcounter<=1281;
                        else
                            pixcounter<=pixcounter+1;    
                        end if;    
                    when st_r3 =>
                        r3<=r3(1 to 1279) & din_w;   
                        if pixcounter=2560 then
                            running2<='1';
                            r1 <= r1(1 to 1279) & r2(0);
                            r2 <= r2(1 to 1279) & r3(0);
                            r3 <= r3(1 to 1279) & din_w; 
                            conv_window <= r1(0 to 2) & r2(0 to 2) & r3(0 to 2); 
                            cnt_col<=cnt_col+1;
                            state<=st_conv;      
                        elsif pixcounter=2559 then
                            running2<='1';
                            conv_window <="00000000" & r1(0 to 1) &  "00000000"   &  r2(0 to 1) &  "00000000" &  r3(1 to 2); -- r3(1 to 2); 0 to 2 için gerekebilir
                            pixcounter<=2560;    
                        else
                            pixcounter<=pixcounter+1;
                        end if;          
                    when st_conv=>
                        r1 <= r1(1 to 1279) & r2(0);
                        r2 <= r2(1 to 1279) & r3(0);
                        r3 <= r3(1 to 1279) & din_w;  
                        if(cnt_col<col-1) then
                            running2<='1';
                            conv_window <= r1(0 to 2) & r2(0 to 2) & r3(0 to 2); 
                        end if;
                        if(cnt_col=col) then  
                            running2<='1';
                            conv_window <="00000000" & r1(1 to 2) & "00000000" & r2(1 to 2)  & "00000000" & r3(1 to 2);
                            cnt_col<=0;
                        else
                            cnt_col<=cnt_col+1;    
                        end if;               
                        if cnt_col=col-1 then
                            running2<='1';
                            conv_window <=r1(0 to 1) & "00000000" &   r2(0 to 1) & "00000000"   &  r3(0 to 1) & "00000000" ;
                        end if;      
                end case;   
            end if;           
        end if;
    end process;
          
    c0: convolution2d port map (
        clk=>clk,
        start=>running2, 
        window => conv_window,
        pixel => dout_W,
        conv_running=>conv_running_o
    );


end rtl;

 

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Teacher
Teacher
412 Views
Registered: ‎07-09-2009

Re: large shift register synthesis issue

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SRL are 32 bit shift registers,
they cascade very nicely.
https://www.xilinx.com/support/documentation/white_papers/wp271.pdf

DO Not set internal signals to 'z'.

you also need to think about resets,
https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

looks to me like your designing as software,
if you want a shift register,
code a shift register,


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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3 Replies
Highlighted
Teacher
Teacher
433 Views
Registered: ‎07-09-2009

Re: large shift register synthesis issue

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r1, r2 r3 are tri state signals as you set them to z by default ?
how are these going to be routed inside the fpga.

Do you know about SRL's in the FPGA.
code to use them, and you get a 32 to 1 size improvement.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
427 Views
Registered: ‎07-26-2018

Re: large shift register synthesis issue

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@drjohnsmith 

Actually, I'm not sure what is the tri state signal. I just set 'Z' to for simulation.
I'll look at what "SRL's" is.
Thank you.

edit: srl depth supports up to 1024. but my r1,r2,r3 has 1279 depth

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Highlighted
Teacher
Teacher
413 Views
Registered: ‎07-09-2009

Re: large shift register synthesis issue

Jump to solution
SRL are 32 bit shift registers,
they cascade very nicely.
https://www.xilinx.com/support/documentation/white_papers/wp271.pdf

DO Not set internal signals to 'z'.

you also need to think about resets,
https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

looks to me like your designing as software,
if you want a shift register,
code a shift register,


<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post