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Anonymous
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malformed $readmem task... why?

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Vivado 2016.3, SystemVerilog source.

 

For this test, I have an inner module and an outer module. The inner module acts like a ROM. The outer module access the ROM. The data for the ROM is in a file.

 

However, in order to promote unit testability on the inner module, I'm passing in the ROM's data to the inner module. I know, that's totally weird, but I'm a software engineer.

 

File inner.sv:

 

module inner(
    input clk,
    input bit[15:0] things[256],
    input bit[7:0] index,
    output bit[15:0] result
);

always_ff @(posedge clk) begin
    result <= things[index];
end

endmodule

File outer.sv:

 

module outer(
    input clk,
    input bit[7:0] index,
    output bit[15:0] result
);

var bit[15:0] things[256];
initial $readmemb("things.data", things);

inner inner(
    .clk,
    .things,
    .index,
    .result
);

endmodule

 

I added things.data as a data file. Unfortunately, I got the dreaded "invalid memory name" which tells you only that something went wrong but not what:

 

WARNING: [Synth 8-2898] ignoring malformed $readmem task: invalid memory name [F:/plugh1/file_test/file_test.srcs/sources_1/new/outer.sv:8]

Sooo....

 

(1) What went wrong? My earlier expeditions basically blamed Vivado for not being able to recognize RAM. But this seems to be a really simple application of RAM.

 

(2) For testability, what would you suggest? I'm using Verilator and writing a C++ test bench, but if I hardcode the ROM in the inner module, it is no longer testable -- all I'd be testing is the production ROM data, not that the module works as intended. Again, sorry, I'm using testability best practices from the software world, and I don't know what the best practice is for this case in the FPGA world.

 

Project attached.

 

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Scholar
Scholar
9,166 Views
Registered: ‎09-16-2009

Re: malformed $readmem task... why?

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Oh, I also now see how you pass the ROM down to inner.  Although legal, it'll probably not synthesize to what you want. 

 

One way to solve this is to declare the ROM 2-d array down in 'inner', then pass in the name of the filename to initialize it with as a parameter to the inner module.

 

If you follow the Xilinx templates, this is entirely synthesizable, and meets your test ability needs.

 

Regards,

 

Mark

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Anonymous
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Re: malformed $readmem task... why?

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Also, yeah, I'm pretty sure passing in the entire contents of the ROM is a terrible idea. Does anyone have any ideas on how you would test that the inner module is working without relying on production ROM data?

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Scholar
Scholar
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Registered: ‎09-16-2009

Re: malformed $readmem task... why?

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@Anonymous wrote:

Vivado 2016.3, SystemVerilog source.

 

 
module outer(
    input clk,
    input bit[7:0] index,
    output bit[15:0] result
);

var bit[15:0] things[256];
initial $readmemb("things.data", things);

inner inner(
    .clk,
    .things,
    .index,
    .result
);

endmodule

 

 

That deceleration for the 2-d array "things" is wrong - it should be:

bit[15:0] things[255:0];

(Note I removed the 'var' - as indicated in the other thread, I'm not sure what it does, it's NOT necessary, and it'll confuse others, and perhaps even the tools, as NO ONE uses it).

 

You need an explicit range in Verilog, NOT a length specifier for all vector declarations.

 

As to your test ability questions, a ROM's rather a simple case.  You basically just want a simulation that runs through a read of all addresses, and compares the actual read data against expected.

 

I imagine what's concerning you is that if you squint, you see yourself, basically doing a "if( 1==1 ) then pass"  Which is kind-of true for a small testcase such as this.  But you'd be surprised on what could go wrong.  I'd have no problem writing, and simulating such a test, and encourage you to continue.

 

Regards,

 

Mark

 

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Scholar
Scholar
9,167 Views
Registered: ‎09-16-2009

Re: malformed $readmem task... why?

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Oh, I also now see how you pass the ROM down to inner.  Although legal, it'll probably not synthesize to what you want. 

 

One way to solve this is to declare the ROM 2-d array down in 'inner', then pass in the name of the filename to initialize it with as a parameter to the inner module.

 

If you follow the Xilinx templates, this is entirely synthesizable, and meets your test ability needs.

 

Regards,

 

Mark

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Anonymous
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Re: malformed $readmem task... why?

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@markcurry wrote:

 

You need an explicit range in Verilog, NOT a length specifier for all vector declarations.


Hmm, no, I'm suspicious. Check out 7.4.2 (unpacked arrays). Specifically, "Each fixed-size dimension shall be represented by an address range, such as [1:1024] , or a single positive number to specify the size of a fixed-size unpacked array, as in C. In other words, [size] becomes the same as [0:size-1] ."

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Anonymous
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Re: malformed $readmem task... why?

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@markcurry wrote:

 

One way to solve this is to declare the ROM 2-d array down in 'inner', then pass in the name of the filename to initialize it with as a parameter to the inner module.

 

 


Ah, now that's a really good idea! Perfect, I'll try that.

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Moderator
Moderator
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Registered: ‎07-01-2015

Re: malformed $readmem task... why?

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Hi @Anonymous,

 

Please go through https://www.xilinx.com/support/answers/63041.html and see if it helps.

Thanks,
Arpan
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Anonymous
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Re: malformed $readmem task... why?

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Hi Arpan,

 

Those might work, but I'll try them only if I've exhausted the solutions that are not vendor-specific. So far I've been lucky in that everything in my project has been done strictly in SystemVerilog.

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