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Observer
Observer
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Registered: ‎12-04-2015

max_fanout sometimes doesn't work in Verilog

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I am using Vivado 216.3 with default settings. The attribute max_fanout works in general, but on one signal it doesn't:

 

(*max_fanout= 8*) reg  lastNow;

 

I see no message in synthesis report and timing  reports says fanout 24;  (I would expect 26)

 

When I change the value to 2, then I do see a message in synthesis report: Fanout is changed from 3 to 2. In timing report it is 24 again. :-)

My guess is that XST makes two internal copies of the signal and assigns the fanout to one of them.

How can I avoid this?

 

When I replicate the register manually (using dont_touch), timing closes and everything is fine.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Observer
Observer
9,357 Views
Registered: ‎12-04-2015

Re: max_fanout sometimes doesn't work in Verilog

Jump to solution

@nupurs wrote:

@uncle_tim,

 

see if this AR helps:
https://www.xilinx.com/support/answers/62162.html


No, sorry. It't all in one hierarchy.

 

I think I have found it. In my opinion this is a bug in XST.

The problem is caused by an inverted clock enable. XST seems to make two signals internally: one inverted and one not inverted. This causes the attribute not to propagate properly.

 

 

The following code reproduces the problem.

 

module Combiner
(
    input wire sysClk,
    input wire [6:0] tag,
    input wire  [16:0] tcounter,
    input wire now,
    output reg [23:0] combinedTag,
    output reg combinedTagWr
);

 

(* max_fanout= 2 *)reg  lastNow;
@always @(posedge sysClk) begin
    if (!lastNow)
        combinedTag<=  {tcounter, tag};
    combinedTagWr<=now  | lastNow;
    lastNow<= now & !lastNow;
end
    
endmodule

 

 

From synth report:
---------------------------------------------------------------------------------
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net lastNow. Fanout reduced from 3 to 2 by creating 1 replicas.
---------------------------------------------------------------------------------

 

Timing says fanout 24.

 

When you remove the inversion in "if (!lastNow)", the problem goes away.

 

 

 

 

View solution in original post

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Moderator
Moderator
5,071 Views
Registered: ‎06-24-2015

Re: max_fanout sometimes doesn't work in Verilog

Jump to solution

@uncle_tim,

 

see if this AR helps:
https://www.xilinx.com/support/answers/62162.html

Thanks,
Nupur
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Observer
Observer
4,749 Views
Registered: ‎12-04-2015

Re: max_fanout sometimes doesn't work in Verilog

Jump to solution

@nupurs wrote:

@uncle_tim,

 

see if this AR helps:
https://www.xilinx.com/support/answers/62162.html


Sorry, no.

The signal is not going to a different hierarchy.

 

It is defined locally in a for loop within a generate block.

 

When I set max_fanout to 2, I get this in synthesis:

INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in12_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in15_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in18_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in21_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in24_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in27_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in9_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in30_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in33_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in36_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in39_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net lastNow. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in6_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in3_in. Fanout reduced from 3 to 2 by creating 1 replicas.
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net p_0_in0_in. Fanout reduced from 3 to 2 by creating 1 replicas.

 

 

In timing report the fanout it 24.

 

First I thought it would be connected to the funny renaming. But pushing definition of the signal outside the for loop (and makig it an array) didn't help.

 

One thing I find interesting: The signal is used as a clock enable 24 times and as a data input 2 times.

For me it looks like the two use cases are mapped to two different signals internally and only one of them gets the attribute attached to it?

 

 

 

 

 

 

 

 

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Highlighted
Observer
Observer
9,358 Views
Registered: ‎12-04-2015

Re: max_fanout sometimes doesn't work in Verilog

Jump to solution

@nupurs wrote:

@uncle_tim,

 

see if this AR helps:
https://www.xilinx.com/support/answers/62162.html


No, sorry. It't all in one hierarchy.

 

I think I have found it. In my opinion this is a bug in XST.

The problem is caused by an inverted clock enable. XST seems to make two signals internally: one inverted and one not inverted. This causes the attribute not to propagate properly.

 

 

The following code reproduces the problem.

 

module Combiner
(
    input wire sysClk,
    input wire [6:0] tag,
    input wire  [16:0] tcounter,
    input wire now,
    output reg [23:0] combinedTag,
    output reg combinedTagWr
);

 

(* max_fanout= 2 *)reg  lastNow;
@always @(posedge sysClk) begin
    if (!lastNow)
        combinedTag<=  {tcounter, tag};
    combinedTagWr<=now  | lastNow;
    lastNow<= now & !lastNow;
end
    
endmodule

 

 

From synth report:
---------------------------------------------------------------------------------
INFO: [Synth 8-4618] Found max_fanout attribute set to 2 on net lastNow. Fanout reduced from 3 to 2 by creating 1 replicas.
---------------------------------------------------------------------------------

 

Timing says fanout 24.

 

When you remove the inversion in "if (!lastNow)", the problem goes away.

 

 

 

 

View solution in original post

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