cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
onkarkk1
Explorer
Explorer
6,576 Views
Registered: ‎12-29-2008

maximum delay from LUT ..

Hi,

Can any one tell me what is maximum delay (ns) from the LUT of virtex - 4 fx -10 FPGA.

 

Thanks in advance,

 

regards,

Krishna Kishore. 

Tags (1)
0 Kudos
4 Replies
eilert
Teacher
Teacher
6,570 Views
Registered: ‎08-14-2007

Hi Krischna,

You will find these values in the static timing analysis report. (also found at the end of the *.syr synthesis report)

When you take a look at the times listed in the critical path (and the other paths too)

You will find entries like LUT2, LUT3, LUT4 wich all have the same gate delay. In addition you find the net delay for the routing from one of these LUTs to another in that list too.

 At the end is a total sum and in brackets the partitiial sums of the gate and net delays (called logic and route here)

 

You will recognize, that elements other than LUTs (e.g. MUXCY, MUXF5 etc.) have different gate delays, but the same for each gate type.

Also it can be observed, that the routing delay nowadays is almost equal or even greater than the gate delay. 

 

Have a nice synthesis

  Eilert

 

 

0 Kudos
onkarkk1
Explorer
Explorer
6,567 Views
Registered: ‎12-29-2008

Thank you Eilert,

 

I found whatever you cited but i didnt find critical path is it seperately mentioned or we have to understand based on delays of the paths, it is showing only 3 paths delays(whatever big the design it is showing only 3 paths delays is it any constraint of the tool).. Please let me..

 

Thanks in advance,

regards,

Krishna Kishore 

 

0 Kudos
bassman59
Historian
Historian
6,558 Views
Registered: ‎02-25-2008


onkarkk1 wrote:

Hi,

Can any one tell me what is maximum delay (ns) from the LUT of virtex - 4 fx -10 FPGA.

 

Thanks in advance,

 

regards,

Krishna Kishore. 


RTFDS.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
evgenis1
Advisor
Advisor
6,553 Views
Registered: ‎12-03-2007

It is showing only 3 paths because this is the default value in ISE. If you go to "Place and Route" -> "Generate Static Timing" menu, and open "Process Properties" dialog, you can select different timing analysis parameters.

 

 

OutputLogic 

Tags (2)
0 Kudos