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ferozalitm
Newbie
Newbie
7,925 Views
Registered: ‎10-21-2009

memory conflict,run out of memory

 

Please help,

When I synthesized my project it compiled,went to Advanced hdl Synthesize ,then showed optimization.thereafter synthesize failed with last message in console as----

"  ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict.  Current memory usage is 4162880 kb.  You can try increasing your system's physical or virtual memory.  For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. "

 

The console shown was as below

 

 

 

 

 

 

Reading design: tb_main.prj

=========================================================================
*                          HDL Compilation                              *
=========================================================================
ompiling vhdl file "C:/doc/project/work/thur21/rand_gen.vhd" in Library work.
Entity <rand_gen> compiled.
Entity <rand_gen> (Architecture <behav>) compiled.
Compiling vhdl file "C:/doc/project/work/thur21/cswRg.vhd" in Library work.
Entity <cswRg> compiled.
Entity <cswRg> (Architecture <behav>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <tb_main> in library <work> (architecture <test>).
nalyzing hierarchy for entity <cord_divo_0> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <cord_divo_1> in library <work> (architecture <behav>).

Analyzing hierarchy for entity <cord_divo_15> in library <work> (architecture <behav>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <tb_main> in library <work> (Architecture <test>).
Entity <tb_main> analyzed. Unit <tb_main> generated.

Analyzing Entity <main> in library <work> (Architecture <struc>).
Entity <main> analyzed. Unit <main> generated.


Analyzing Entity <csw2> in library <work> (Architecture <behav>).
WARNING:Xst:790 - "C:/doc/project/work/thur21/csw2.vhd" line 28: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/doc/project/work/thur21/csw2.vhd" line 32: Index value(s) does not match array range, simulation mismatch.
Entity <csw2> analyzed. Unit <csw2> generated.

Analyzing Entity <M1> in library <work> (Architecture <behav>).
WARNING:Xst:790 - "C:/doc/project/work/thur21/M1.vhd" line 27: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/doc/project/work/thur21/M1.vhd" line 31: Index value(s) does not match array range, simulation mismatch.
Entity <M1> analyzed. Unit <M1> generated.

Analyzing Entity <M2> in library <work> (Architecture <behav>).
WARNING:Xst:790 - "C:/doc/project/work/thur21/M2.vhd" line 26: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/doc/project/work/thur21/M2.vhd" line 30: Index value(s) does not match array range, simulation mismatch.

Analyzing Entity <cont_resamp2> in library <work> (Architecture <behav>).
WARNING:Xst:819 - "C:/doc/project/work/thur21/cont_resamp2.vhd" line 75: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
   <countr>, <countj>
Entity <cont_resamp2> analyzed. Unit <cont_resamp2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <zmem>.
    Related source file is "C:/doc/project/work/thur21/zm_mem.vhd".

Synthesizing Unit <extMm>.
    Related source file is "C:/doc/project/work/thur21/extRg.vhd".
    Found 16-bit register for signal <outp>.
    Found 160-bit register for signal <dat>.
    Found 16-bit 10-to-1 multiplexer for signal <outp$mux0000> created at line 31.
Unit <extMm> synthesized.

    inferred   1 D-type flip-flop(s).
    inferred   3 Adder/Subtractor(s).
    inferred   1 Xor(s).
Unit <cord_mult> synthesized.


Synthesizing Unit <cordic_outx>.
    Related source file is "C:/doc/project/work/thur21/cordic_outx.vhd".
ignal <xt$addsub0000> created at line 66.  Found 25-bit adder for signal <yt$addsub0000> created at line 71.  Summary:
    inferred   3 Adder/Subtractor(s).
    inferred   1 Xor(s).
Unit <cordic_outx> synthesized.


Synthesizing Unit <cordic_outy>.
    Related source file is "C:/doc/project/work/thur21/cordic_outy.vhd".
WARNING:Xst:737 - Found 1-bit latch for signal <sign>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as thnal <xt$addsub0000> created at line 66.  Found 25-bit adder for signal <yt$addsub0000> created at line 71.  Summary:
    inferred   3 Adder/Subtractor(s).
    inferred   1 Xor(s).
Unit <cordic_outy> synthesized.


Synthesizing Unit <cordic_outvx>.
    Related source file is "C:/doc/project/work/thur21/cordic_outvx.vhd".
WARNING:Xst:737 - Found 1-bit latch for signal <sign>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <outp>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 25-bit latch for signal <xt>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 25-bit latch for signal <yt>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.  Found 16-bit adder for signal <outp$addsub0000> created at line 96.  Found 1-bit xor2 for signal <sign$xor0000> created at line 75.  Found 25-bit adder for signal <xt$addsub0000> created at line 66.  Found 25-bit adder for signal <yt$addsub0000> created at line 71.  Summary:
    inferred   3 Adder/Subtractor(s).
    inferred   1 Xor(s).
Unit <cordic_outvx> synthesized.


Synthesizing Unit <cordic_outvy>.
    Related source file is "C:/doc/project/work/thur21/cordic_outvy.vhd".
WARNING:Xst:737 - Found 1-bit latch for signal <sign>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 16-bit latch for signal <outp>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 25-bit latch for signal <xt>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 25-bit latch for signal <yt>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.  Found 16-bit adder for signal <outp$addsub0000> created at line 96.  Found 1-bit xor2 for signal <sign$xor0000> created at line 75.  Found 25-bit adder for signal <xt$addsub0000> created at line 66.  Found 25-bit adder for signal <yt$addsub0000> created at line 71.  Summary:
    inferred   3 Adder/Subtractor(s).
    inferred   1 Xor(s).
Unit <cordic_outvy> synthesized.


Synthesizing Unit <cord_divo>.
    Related source file is "C:/doc/project/work/thur21/cord_divo.vhd".
WARNING:Xst:647 - Input <ena> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ena2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is

Synthesizing Unit <rand_gen1>.
    Related source file is "C:/doc/project/work/thur21/rand_gen1.vhd".
WARNING:Xst:737 - Found 7-bit latch for signal <seed11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, ARNING:Xst:737 - Found 7-bit latch for signal <rnd2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.  Found 1-bit xor2 for signal <result0_6$xor0000> created at line 239.  Found 1-bit xor4 for signal <result1_15$xor0000> created at line 253.  Found 1-bit xor4 for signal <result2_15$xor0000> created at line 253.  Found 1-bit xor2 for signal <result_6$xor0000> created at line 239.  Su
mmary:
    inferred   2 Xor(s).
Unit <rand_gen1> synthesized.


Synthesizing Unit <rand_gen2>.
    Related source file is "C:/doc/project/work/thur21/rand_gen2.vhd".
WARNING:Xst:737 - Found 7-bit latch for signal <seed11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 7-bit latch for signal <rnd2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
    Found 1-bit xor2 for signal <result0_6$xor0000> created at line 239.
    Found 1-bit xor4 for signal <result1_15$xor0000> created at line 253.
    Found 1-bit xor4 for signal <result2_15$xor0000> created at line 253.
    Found 1-bit xor2 for signal <result_6$xor0000> created at line 239.
    Summary:
    inferred   2 Xor(s).
Unit <rand_gen2> synthesized.


Synthesizing Unit <gaussian>.
    Related source file is "C:/doc/project/work/thur21/gaussian.vhd".
Unit <gaussian> synthesized.


Synthesizing Unit <multiplier>.
    Related source file is "C:/doc/project/work/thur21/multiplier.vhd".
Unit <multiplier> synthesized.


Synthesizing Unit <outCalc>.
    Related source file is "C:/doc/project/work/thur21/outCalc.vhd".
Unit <outCalc> synthesized.


Synthesizing Unit <normalize>.
    Related source file is "C:/doc/project/work/thur21/normalize.vhd".
WARNING:Xst:653 - Signal <w1<24:16>> is used but never assigned. This sourceless signal will be automatically connected to value 000000000.
Unit <normalize> synthesized.


Synthesizing Unit <main>.
    Related source file is "C:/doc/project/work/thur21/main.vhd".
WARNING:Xst:647 - Input <zin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <z_msr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <adrwsx2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <adrwsx1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <main> synthesized.


Synthesizing Unit <tb_main>.
    Related source file is "C:/doc/project/work/thur21/tb_main.vhd".
WARNING:Xst:646 - Signal <y_out> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <x_out> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    inferred   1 Comparator(s).
Unit <tb_main> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 7
 128x32-bit ROM                                        : 4
 30x16-bit ROM                                         : 1
 512x16-bit ROM                                        : 2
# Adders/Subtractors                                   : 1052
 10-bit adder                                          : 9
 10-bit subtractor                                     : 4
 16-bit adder                                          : 64
 16-bit addsub                                         : 756
 16-bit subtractor                                     : 26
 17-bit addsub                                         : 56
 17-bit subtractor                                     : 4
 25-bit adder                                          : 13
 25-bit addsub                                         : 84
 25-bit subtractor                                     : 6
 31-bit adder                                          : 2
 4-bit adder                                           : 28
# Accumulators                                         : 12
 16-bit up accumulator                                 : 2
 25-bit up accumulator                                 : 10
# Registers                                            : 14194
 1-bit register                                        : 16
 16-bit register                                       : 14018
 17-bit register                                       : 60
 25-bit register                                       : 100
# Latches                                              : 1146
 1-bit latch                                           : 9
 10-bit latch                                          : 28
 16-bit latch                                          : 1080
 25-bit latch                                          : 13
 31-bit latch                                          : 2
 4-bit latch                                           : 4
 7-bit latch                                           : 10
# Comparators                                          : 30
 10-bit comparator greater                             : 3
 10-bit comparator less                                : 4
 10-bit comparator lessequal                           : 2
 11-bit comparator greatequal                          : 3
 11-bit comparator less                                : 5
 16-bit comparator equal                               : 1
 16-bit comparator greatequal                          : 8
 16-bit comparator greater                             : 2
 31-bit comparator less                                : 2
# Multiplexers                                         : 122
 16-bit 10-to-1 multiplexer                            : 9
 16-bit 16-to-1 multiplexer                            : 86
 16-bit 512-to-1 multiplexer                           : 27
# Xors                                                 : 22
 1-bit xor2                                            : 18
 1-bit xor4                                            : 4

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

WARNING:Xst:1290 - Hierarchical block <u> is unconnected in block <tb_main>. It will be removed from the design.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 7
 128x32-bit ROM                                        : 4
 30x16-bit ROM                                         : 1
 512x16-bit ROM                                        : 2
# Adders/Subtractors                                   : 1052
 10-bit adder                                          : 9
 10-bit subtractor                                     : 4
 16-bit adder                                          : 64
 16-bit addsub                                         : 756
 16-bit subtractor                                     : 26
 17-bit addsub                                         : 56
 17-bit subtractor                                     : 4
 25-bit adder                                          : 13
 25-bit addsub                                         : 84
 25-bit subtractor                                     : 6
 31-bit adder                                          : 2
 4-bit adder                                           : 28
# Accumulators                                         : 12
 16-bit up accumulator                                 : 2
 25-bit up accumulator                                 : 10
# Registers                                            : 16
 Flip-Flops                                            : 16
# Latches                                              : 1146
 1-bit latch                                           : 9
 10-bit latch                                          : 28
 16-bit latch                                          : 1080
 25-bit latch                                          : 13
 31-bit latch                                          : 2
 4-bit latch                                           : 4
 7-bit latch                                           : 10
# Comparators                                          : 1
 16-bit comparator equal                               : 1
# Multiplexers                                         : 122
 16-bit 10-to-1 multiplexer                            : 9
 16-bit 16-to-1 multiplexer                            : 86
 16-bit 512-to-1 multiplexer                           : 27
# Xors                                                 : 4
 1-bit xor4                                            : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <xt_6> (without init value) has a constant value of 0 in block <cord_mult_gaus>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <s_nxt_mux0002_0> in Unit <cont_samp> is equivalent to the following 3 FFs/Latches, which will be removed : <s_nxt_mux0002_1> <s_nxt_mux0002_2> <s_nxt_mux0002_3>
INFO:Xst:2261 - The FF/Latch <x_tmp_16> in Unit <cord_div_rn1> is equivalent to the following 2 FFs/Latches, which will be removed : <x_tmp_15> <x_tmp_14>
INFO:Xst:2261 - The FF/Latch <x_tmp_15> in Unit <cord_mult_1> is equivalent to the following 2 FFs/Latches, which will be removed : <x_tmp_14> <x_tmp_13>
INFO:Xst:2261 - The FF/Latch <x_tmp_15> in Unit <cord_div_1> is equivalent to the following 2 FFs/Latches, which will be removed : <x_tmp_14> <x_tmp_13>
INFO:Xst:2261 - The FF/Latch <seed22_15> in Unit <rand_gen1> is equivalent to the following FF/Latch, which will be removed : <inp2_15>
INFO:Xst:2261 - The FF/Latch <seed22_12> in Unit <rand_gen1> is equivalent to the following FF/Latch, which will be removed : <inp2_12>
INFO:Xst:2261 - The FF/Latch <seed21_5> in Unit <rand_gen1> is equivalent to the following FF/Latch, which will be removed : <rnd2_5>
INFO:Xst:2261 - The FF/Latch <seed21_2> in Unit <rand_gen1> is equivalent to the following FF/Latch, which will be removed : <rnd2_2>
INFO:Xst:2261 - The FF/Latch <seed12_12> in Unit <rand_gen1> is equivalent to the following FF/Latch, which will be removed : <inp1_12>
IINFO:Xst:2261 - The FF/Latch <seed11_6> in Unit <rand_gen2> is equivalent to the following FF/Latch, which will be removed : <rnd1_6>
INFO:Xst:2261 - The FF/Latch <seed12_2> in Unit <rand_gen2> is equivalent to the following FF/Latch, which will be removed : <inp1_2>

Optimizing unit <tb_main> ...

Optimizing unit <mux201> ...

Optimizing unit <stat> ...

Optimizing unit <rndMm1> ...

Optimizing unit <rndMm2> ...

Optimizing unit <compar> ...

Optimizing unit <zmem> ...

Optimizing unit <wiMm> ...

Optimizing unit <csw1> ...

Optimizing unit <M2> ...

Optimizing unit <samp_mem> ...

Optimizing unit <extMm> ...

Optimizing unit <cont_samp> ...

Optimizing unit <cont_resamp1> ...
WARNING:Xst:1710 - FF/Latch <addr_sx_9> (without init value) has a constant value of 0 in block <cont_resamp1>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <cont_resamp2> ...

Optimizing unit <cord_div_rn0> ...

Optimizing unit <cord_mult_0> ...

Optimizing unit <cord_atan_15> ...

Optimizing unit <cord_div_0> ...

Optimizing unit <cord_exp_0> ...

Optimizing unit <sampler> ...

Optimizing unit <prAdd> ...

Optimizing unit <wtAdd> ...

Optimizing unit <csw2> ...

Optimizing unit <M1> ...

Optimizing unit <cord_div_rn1> ...

Optimizing unit <cord_div_rn15> ...

Optimizing unit <cord_mult_1> ...

Optimizing unit <cord_mult_15> ...

Optimizing unit <cord_atan_0> ...

Optimizing unit <cord_atan_1> ...

Optimizing unit <cord_div_1> ...

Optimizing unit <cord_div_15> ...

Optimizing unit <cord_exp_1> ...

Optimizing unit <cord_exp_15> ...

Optimizing unit <cord_divo_0> ...
  implementation constraint: INIT=r     : y_tmp_24
  implementation constraint: INIT=r     : y_tmp_0
  implementation constraint: INIT=r     : y_tmp_1
  implementation constraint: INIT=r     : y_tmp_2
  implementation constraint: INIT=r     : y_tmp_3
  implementation constraint: INIT=r     : y_tmp_4
  implementation constraint: INIT=r     : y_tmp_5
  implementation constraint: INIT=r     : y_tmp_6
  implementation constraint: INIT=r     : y_tmp_7
  implementation constraint: INIT=r     : y_tmp_8
  implementation constraint: INIT=r     : y_tmp_9
  implementation constraint: INIT=r     : y_tmp_10
  implementation constraint: INIT=r     : y_tmp_11
  implementation constraint: INIT=r     : y_tmp_12
  implementation constraint: INIT=r     : y_tmp_13
  implementation constraint: INIT=r     : y_tmp_14
  implementation constraint: INIT=r     : y_tmp_15
  implementation constraint: INIT=r     : y_tmp_16
  implementation constraint: INIT=r     : y_tmp_17
  implementation constraint: INIT=r     : y_tmp_18
  implementation constraint: INIT=r     : y_tmp_19
  implementation constraint: INIT=r     : y_tmp_20
  implementation constraint: INIT=r     : y_tmp_21
  implementation constraint: INIT=r     : y_tmp_22
  implementation constraint: INIT=r     : y_tmp_23
  implementation constraint: INIT=r     : z_tmp_14

Optimizing unit <cord_divo_1> ...

Optimizing unit <cord_divo_15> ...

Optimizing unit <prAcc> ...

Optimizing unit <wtAcc> ...

Optimizing unit <wnAdd> ...

Optimizing unit <inv_tan> ...

Optimizing unit <square> ...

Optimizing unit <div> ...

Optimizing unit <exp> ...

Optimizing unit <cord_div_rnd> ...

Optimizing unit <cord_mult_gaus> ...

Optimizing unit <cord_mult> ...

Optimizing unit <cordic_outx> ...

Optimizing unit <cordic_outy> ...

Optimizing unit <cordic_outvx> ...

Optimizing unit <cordic_outvy> ...

Optimizing unit <cord_divo> ...

Optimizing unit <rand_gen1> ...

Optimizing unit <rand_gen2> ...

Optimizing unit <gaussian> ...

Optimizing unit <multiplier> ...

Optimizing unit <outCalc> ...

Optimizing unit <normalize> ...

Optimizing unit <main> ...
ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict.  Current memory usage is 4162880 kb.  You can try increasing your system's physical or virtual memory.  For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Synthesis" failed
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5 Replies
jprovidenza
Voyager
Voyager
7,919 Views
Registered: ‎08-30-2007

This probably won't help your problem... but did you notice that the synthesizer

is warning you about a lot of latches being infered?  Do you really want latches?

 

You may want to clean up the code to eliminate them, then see what happens.

 

John Providenza

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ferozalitm
Newbie
Newbie
7,907 Views
Registered: ‎10-21-2009

Thank You,

But this project was already compiled and Synthesized successfully by a senior student. hence the code is not supposed to be changed since he successfully downloaded it to Vertex Pro 2.

Can you give any suggestion to make the synthesis successful.

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jprovidenza
Voyager
Voyager
7,893 Views
Registered: ‎08-30-2007

You might try playing with the synthesis options.  Do you have "keep hierarchy" on or off?

 

BTW - if someone came to me with any latches in a design, they'd have to do a lot of

explaining to justify them.  Sometime they're needed, but most of the time they are the

result of coding errors.  I can't think of the last time I used a latch in any FPGA design.

 

 

John Providenza

 

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hobson
Xilinx Employee
Xilinx Employee
7,840 Views
Registered: ‎04-15-2008

My guess is that the high memory utilization for such a small design is due to XST seeing coding structures it doesn't recognize and therefore churning on that logic.  The latches that John mentions could possibly be a part of that.

 

Even if you were to submit this to Tech Support, Virtex-II Pro is no longer a target in the latest software version (11.3), so no software fix would be forthcoming if this was, in fact, a bug.

 

If you can't modify the code, I suggest doing 1 of 2 things:

1) Run the design on a 64-bit machine with more memory.

2) Synthesize some of the modules separately and then allow NGDBUILD to pull all the synthesis netlists (NGC files) back together.  This breaks up synthesis into smaller chunks which will hopefully let you work around the out-of-memory problem.  Just make sure you don't insert I/Os when synthesizing any lower level modules.

 

Regards,

-Hobson

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ferozalitm
Newbie
Newbie
7,688 Views
Registered: ‎10-21-2009

Thank You

My problem of out of memory got fixed.I tried to synthesis some modules separately,it worked.When I used the proper device version of vertex 2 pro in the device selecting option,all my modules got synthesized properly.

 

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