10-21-2009 11:10 AM
When I synthesized my project it compiled,went to Advanced hdl Synthesize ,then showed optimization.thereafter synthesize failed with last message in console as----
" ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 4162880 kb. You can try increasing your system's physical or virtual memory. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. "
The console shown was as below
Reading design: tb_main.prj
10-21-2009 12:02 PM
This probably won't help your problem... but did you notice that the synthesizer
is warning you about a lot of latches being infered? Do you really want latches?
You may want to clean up the code to eliminate them, then see what happens.
10-22-2009 12:45 AM
But this project was already compiled and Synthesized successfully by a senior student. hence the code is not supposed to be changed since he successfully downloaded it to Vertex Pro 2.
Can you give any suggestion to make the synthesis successful.
10-22-2009 08:36 AM
You might try playing with the synthesis options. Do you have "keep hierarchy" on or off?
BTW - if someone came to me with any latches in a design, they'd have to do a lot of
explaining to justify them. Sometime they're needed, but most of the time they are the
result of coding errors. I can't think of the last time I used a latch in any FPGA design.
10-27-2009 08:42 PM
My guess is that the high memory utilization for such a small design is due to XST seeing coding structures it doesn't recognize and therefore churning on that logic. The latches that John mentions could possibly be a part of that.
Even if you were to submit this to Tech Support, Virtex-II Pro is no longer a target in the latest software version (11.3), so no software fix would be forthcoming if this was, in fact, a bug.
If you can't modify the code, I suggest doing 1 of 2 things:
1) Run the design on a 64-bit machine with more memory.
2) Synthesize some of the modules separately and then allow NGDBUILD to pull all the synthesis netlists (NGC files) back together. This breaks up synthesis into smaller chunks which will hopefully let you work around the out-of-memory problem. Just make sure you don't insert I/Os when synthesizing any lower level modules.
11-10-2009 08:00 PM
My problem of out of memory got fixed.I tried to synthesis some modules separately,it worked.When I used the proper device version of vertex 2 pro in the device selecting option,all my modules got synthesized properly.