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Registered: ‎03-30-2017

module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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I'm following these instructions. I'm right at the beginning, attempting to generate a bit stream (see section Build Flow Tutorials, subsection PL Base TRD). During the synthesis I'm getting the following error: zcu102_not_found.png

I'm not quite sure how to fix it. Has anyone seen it before?

 

Any help is appreciated.

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Registered: ‎03-30-2017

Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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Reinstalled all the software. Removed and reinstalled SDK and SDx, and followed the same instructions again. Everything started working. Don't know what was the issue.

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Scholar
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Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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@rail.shafigulin

Did you look into the console or run log file for more details? 

 

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Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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Yes. Here is what I got in a runme.log for this component.

 

 

*** Running vivado
    with args -log zcu102_base_trd_zynq_ultra_ps_e_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source zcu102_base_trd_zynq_ultra_ps_e_0_0.tcl



****** Vivado v2016.4_sdx (64-bit)
  **** SW Build 1806307 on Thu Mar  9 15:24:27 MST 2017
  **** IP Build 1759159 on Thu Jan 26 07:31:30 MST 2017
    ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

Sourcing tcl script '/home/user/myfs/pkg/Xilinx/SDx/2016.4/Vivado/scripts/init.tcl'
16 Beta devices matching pattern found, 16 enabled.
Loaded SDSoC Platform Tcl Library
source zcu102_base_trd_zynq_ultra_ps_e_0_0.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1482.340 ; gain = 550.953 ; free physical = 2837 ; free virtual = 11406
ERROR: [Synth 8-439] module 'zcu102_base_trd_zynq_ultra_ps_e_0_0' not found
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1522.809 ; gain = 591.422 ; free physical = 2796 ; free virtual = 11365
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

Is there any other place I need to look at? 

 

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Scholar
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Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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@rail.shafigulin Yes, go to the TCL console and type `pwd`

That will give a folder path. 

Go there and look for the most recent log files. 

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Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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Hi @rail.shafigulin,

 

Which instruction exactly did you do?

 

Are you running from the correct path?

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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Here is the output of pwd in the TCL console

 

/home/user/projects/myproject/rdf0421-zcu102-base-trd-2016-4/pl/zcu102_base_trd

Seems correct to me, but this is me first time using Vivado, so I could be wrong.

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Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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@florentw The path I'm running from is

/home/user/projects/myproject/rdf0421-zcu102-base-trd-2016-4/pl/zcu102_base_trd

 

The instructions I've executed are:

0.

source /home/user/myfs/pkg/Xilinx/SDx/2016.4/settings64.sh 

1.

% cd $TRD_HOME/pl/zcu102_base_trd
% vivado -s ./scripts/create_project.tcl -tclargs -platform zcu102 -silicon es2

 2. Generate bit stream

 

Is there anything I'm missing?

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Registered: ‎03-30-2017

Re: module 'zcu102_base_trd_zynq_ultra_ps_e_0_0'

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Reinstalled all the software. Removed and reinstalled SDK and SDx, and followed the same instructions again. Everything started working. Don't know what was the issue.

View solution in original post

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