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aleksazr
Contributor
Contributor
19,635 Views
Registered: ‎09-05-2008

numeric_std, std_logic_vector to integer

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code snipets:

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TEST is port (
     addr : in integer range 0 to 31;
end TEST;

component TEST port (
      addr : in integer range 0 to 31;
end component;



DBUS : inout std_logic_vector(15 downto 0);

Inst_TEST: TEST port map (
addr => to_integer(unsigned(DBUS(4 downto 0))),
);

This is where I get the ISE error:
Actual, ParameterAssocOp, associated with
Formal Signal, Signal 'addr', is not a Signal. (LRM 2.1.1)


What am I doing wrong here?

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1 Solution

Accepted Solutions
gszakacs
Professor
Professor
29,733 Views
Registered: ‎08-14-2007

You can't put the conversion right in the port mapping.  Fist define a signal like:

 

signal addr_i : integer range 0 to 31;

 

then make the assignment

 

addr_i <= to_integer(unsigned(DBUS(4 downto 0)));

 

Then map the port

 

  addr =>  addr_i,

 

 

-- Gabor

-- Gabor

View solution in original post

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2 Replies
gszakacs
Professor
Professor
29,734 Views
Registered: ‎08-14-2007

You can't put the conversion right in the port mapping.  Fist define a signal like:

 

signal addr_i : integer range 0 to 31;

 

then make the assignment

 

addr_i <= to_integer(unsigned(DBUS(4 downto 0)));

 

Then map the port

 

  addr =>  addr_i,

 

 

-- Gabor

-- Gabor

View solution in original post

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aleksazr
Contributor
Contributor
19,621 Views
Registered: ‎09-05-2008
Oh, thank you very much.
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