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Explorer
Explorer
1,408 Views
Registered: ‎08-16-2017

over utilization of DSP blocks

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Hello everyone.

 

I have synthesized a design in Vivado 2017.4.

The utilization report says that - over utilization of DSP blocks. I also see there is under utilization of the LUTs (< 1%).

Is there a way I can map the rest of the design using the LUTS?

I have attached the synthesis reports.

 

Thank you.

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1 Solution

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Scholar jmcclusk
Scholar
1,910 Views
Registered: ‎02-24-2014

Re: over utilization of DSP blocks

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Go to Tools -> Settings, and then select the project settings for Synthesis.     In the option list, set -max_dsp to the maximum number of DSP48's that you want to use. 

 

OR

 

In the TCL console,  give this command (for 333 maximum DSP48's):

 

set_property STEPS.SYNTH_DESIGN.ARGS.MAX_DSP 333 [get_runs synth_1]

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5 Replies
Scholar jmcclusk
Scholar
1,911 Views
Registered: ‎02-24-2014

Re: over utilization of DSP blocks

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Go to Tools -> Settings, and then select the project settings for Synthesis.     In the option list, set -max_dsp to the maximum number of DSP48's that you want to use. 

 

OR

 

In the TCL console,  give this command (for 333 maximum DSP48's):

 

set_property STEPS.SYNTH_DESIGN.ARGS.MAX_DSP 333 [get_runs synth_1]

Don't forget to close a thread when possible by accepting a post as a solution.
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Explorer
Explorer
1,389 Views
Registered: ‎08-16-2017

Re: over utilization of DSP blocks

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Hi @jmcclusk

 

Thank you! The FPGA I am using has 240 DSP blocks. Are DSP and DSP48 the same? 

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Scholar jmcclusk
Scholar
1,386 Views
Registered: ‎02-24-2014

Re: over utilization of DSP blocks

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yes,  DSP48 and DSP are the same.

Don't forget to close a thread when possible by accepting a post as a solution.
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Explorer
Explorer
1,379 Views
Registered: ‎08-16-2017

Re: over utilization of DSP blocks

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Cool. Thank you.

It worked!

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Xilinx Employee
Xilinx Employee
1,349 Views
Registered: ‎08-01-2008

Re: over utilization of DSP blocks

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please refer this document for design closer

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug906-vivado-design-analysis.pdf

You can follow the steps below to generate a module level utilization report.

  1. Run Implementation and open the implemented design.
  2. Click Tools --> Report Utilization. This directs you to a dialog box. Click OK.
  3. This opens a window at the bottom of the Vivado IDE where you can see module level utilization.

 

If you want to export the module level utilization to a report file, you can use the below command in the Tcl console of Vivado:

report_utilization -hierarchical  -file location_of_the_report_file

To report the utilization of a specific cell, use the report_utilization Tcl command as follows:

report_utilization -cells sub_module_name

or

report_utilization -cells [get_cells sub_module_name]

 

 

 

Thanks and Regards
Balkrishan
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