**UPGRADE YOUR BROWSER**

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Turn on suggestions

Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

Showing results for

- Community Forums
- :
- Forums
- :
- Vivado RTL Development
- :
- Synthesis
- :
- Re: overall estimation of a design before even bui...

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Mute
- Printer Friendly Page

varshajhapillai

Visitor

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

03-22-2018 02:23 AM

1,099 Views

Registered:
03-15-2018

Hello,

Have an algorithm which has x Multiplications,

y additions and z memory locations to access.

Using the multiplier ip and the adder ip,

was able to estimate the resource required

for x muls, y adds and no. of BRAMs for

the memory requirement.

(Its a rough estimate) to see if the algorithm

fits in the device.

Got few numbers for these.

Now, want to know the clk cycles for the algorithm.

Is it possible to estimate from this context of ips and

their resource usage, the estimate of the clk cycles

Many thanks in advance,

Varsha

1 Solution

Accepted Solutions

Highlighted

guillaumebres

Scholar

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

03-22-2018 02:49 AM - edited 03-22-2018 02:50 AM

1,429 Views

Registered:
03-27-2014

the number of clock cycles for the maths will be easy to deduce because it only depends on the dynamic range. Say you can perform 16x16 with one slice in two clock cycles, you would need two slices to perform 32x16 and so, four clock cycles.

Assuming (+) is performed with LUT, you can estimate it to one cycle and does not depend on the precision.

The cycles are perfectly deterministic and from your pipeline schematic, you get the exact number of clock cycles.

Now for memory accesses, it gets more complicated because it depends on your interface, the data format and protocol. But if you know the selected interface fairly well, you know how many cycles are required to read and to write.

G.W.,

NIST - Time Frequency metrology

NIST - Time Frequency metrology

4 Replies

Highlighted

guillaumebres

Scholar

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

03-22-2018 02:49 AM - edited 03-22-2018 02:50 AM

1,430 Views

Registered:
03-27-2014

the number of clock cycles for the maths will be easy to deduce because it only depends on the dynamic range. Say you can perform 16x16 with one slice in two clock cycles, you would need two slices to perform 32x16 and so, four clock cycles.

Assuming (+) is performed with LUT, you can estimate it to one cycle and does not depend on the precision.

The cycles are perfectly deterministic and from your pipeline schematic, you get the exact number of clock cycles.

Now for memory accesses, it gets more complicated because it depends on your interface, the data format and protocol. But if you know the selected interface fairly well, you know how many cycles are required to read and to write.

G.W.,

NIST - Time Frequency metrology

NIST - Time Frequency metrology

varshajhapillai

Visitor

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

03-23-2018 12:30 AM

1,057 Views

Registered:
03-15-2018

Re: overall estimation of a design before even building it

Thank you so much for the reply.

Could you help me here if possible.

The multiplier ip works at say xMHz,

the adder ip works at say yMHx and

I need an estimated bunch of these in my design.

Can I estimate the frequency of my design

roughly from this (to estimate power from

the xilinx power estimator tool).

There seems an option of giving the ip and

its freq to estimate the power in the tool as far

as I understand it.

Many thanks again,

Varsha

guillaumebres

Scholar

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

03-23-2018 02:10 AM - edited 03-23-2018 02:12 AM

1,048 Views

Registered:
03-27-2014

Re: overall estimation of a design before even building it

I don't know much about power estimation, I never had to deal with it. Is that your main goal in all of this? because if so, I guess you can directly use "Power Estimation" in Vivado, once your design has been implemented. It surely depends on the design frequency but it also depends on the footprint and routing.

As far as frequencies go,

" The multiplier ip works at say xMHz, the adder ip works at say yMHz ..."

#1 I would not think of it that way. First of all, the best thing to do is to have a single clock domain for all your maths. Everything should be synchronous to one clock. Then, I would rather think in terms of clock cycles. How many cycles does it take to perform step A then B etc.. and go through the whole pipeline.

#2 So saying the multiplier works at 300 MHz and the adder works at 100 MHz does not make sense to me because they will be clocked at the same rate. Once you know the number of cycles and defined the clock frequency, you get the pipeline latency: how long it takes to produce something.

#3 from the system datasheet, you know for instance the multiplier maximum frequency (~500 MHz on 7 serie). From this value, you know the maximum rate you can clock the multiplier at. But it's not the overall pipeline limitation, because the multiplier is the most performant piece of your pipeline. Flip-flops and LUTs are much slower. To get a fair overall estimate, the best thing to do is to write down your pipeline, write proper timing constraints and work on implementation & timing results.

So, if you are only interested in power estimation, I doubt all these steps will help because there's a lot more involved in it. If you are anyway interested in defining timing properly, #1 gives you latency and dead time estimates, #2 turns these values into time and #3 gives you the limitations

G.W.,

NIST - Time Frequency metrology

NIST - Time Frequency metrology

varshajhapillai

Visitor

- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Email to a Friend
- Report Inappropriate Content

03-23-2018 03:23 AM

1,038 Views

Registered:
03-15-2018

Re: overall estimation of a design before even building it

Thank you so much again.

Am bit more clear now that

I could estimate only the resource

(LUTs and FFs) and not beyond that.

Frequency(influenced by the slowest

path) cannot be estimated apriori.

My overall objective is to check

if it is feasible to estimate

the resource, clk cycles, frequency,

power of a given algorithm without

actually designing in to see if fpga is

my desired implementation platform.

My overall design is power constrained.

Varsha