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ahmed_alfadhel
Explorer
Explorer
687 Views
Registered: ‎10-16-2018

overloaded "NOT" gate

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Hi there ,

the code below is for a function which I wrote in VHDL for overloading NOT gate .

The function makes the NOT gate accepts integer input , such as NOT 8 = 7 , for 4 bits integer.

 

 

 

----package of NOT gate for intgers -----
-- Library's ---------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-------------------------------
----package declarations ------------------
Package not_package IS
Function "NOT" (a : integer)
    return integer;
END not_package;
---------------------------------------------
----------- package body---------------------
Package Body not_package is
 Function "NOT" (a: integer)
   return integer is
   
   variable x : std_logic_vector(3 downto 0);
   variable result_logic : std_logic_vector(3 downto 0);
   variable result_integer: integer range 0 to 15;   
   
   x := std_logic_vector(to_unsigned(a , x'length));
   
   result_logic := NOT (x);
   
   result_integer := to_integer(unsigned(result_logic));
   
   return result_integer;
 end "NOT";
end not_package;   

 

 

But, the line 22 ( x := std_logic_vector(to_unsigned(a , x'length));  ) shows an error , and I don't know what is the reason ?

Kindly, see the attached picture from Vivado IDE.

Thanks .

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Accepted Solutions
varunra
Xilinx Employee
Xilinx Employee
657 Views
Registered: ‎01-24-2017

Hi @ahmed_alfadhel ,

There is a syntax error in your code, their is a missing begin in your function. try adding a begin after all of your variable decleration and try. That should work.

Function "NOT1" (a: integer)
return integer is

variable x : std_logic_vector(3 downto 0);
variable result_logic : std_logic_vector(3 downto 0);
variable result_integer: integer range 0 to 15;
begin

Let me know if it works.

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5 Replies
drjohnsmith
Teacher
Teacher
662 Views
Registered: ‎07-09-2009

A quick check

  does length work for a variable ? I have only used it on signals, just give it a go see.

 

 

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varunra
Xilinx Employee
Xilinx Employee
658 Views
Registered: ‎01-24-2017

Hi @ahmed_alfadhel ,

There is a syntax error in your code, their is a missing begin in your function. try adding a begin after all of your variable decleration and try. That should work.

Function "NOT1" (a: integer)
return integer is

variable x : std_logic_vector(3 downto 0);
variable result_logic : std_logic_vector(3 downto 0);
variable result_integer: integer range 0 to 15;
begin

Let me know if it works.

View solution in original post

richardhead
Scholar
Scholar
610 Views
Registered: ‎08-01-2012

@drjohnsmith 

Yes. The 'length attribute is an array attribute. So it doesnt matter if the object is a constant, variable or signal. (others are 'left, right, high, low, ascending, descending)

@ahmed_alfadhel 

Your "not" function allows an integer of any lenght, but only returns 4 bits. If a user inputs 31, it will return 0. Also, if a user inputs a negative number, it with throw an error because you used to_unsigned() for the conversion.

I suggest limiting the range of your not function to be 0 to 15:

 

function "not" (a : natural range 0 to 15) is

 

That way, a user can only input a value that will return a correct result.

ahmed_alfadhel
Explorer
Explorer
574 Views
Registered: ‎10-16-2018

Thanks @varunra ,

I just was need the "begin" statement .

I am grateful for you.

ahmed_alfadhel
Explorer
Explorer
566 Views
Registered: ‎10-16-2018

Hi @richardhead ,

Thanks to your reply.

About the range constraint in Function. I didn't indicate it deliberately, since I read that in Pedroni book "Circuit Design with VHDL" .

When I input 31 , Vivado Simulator throws an error , indicating that 31 is out of range .

Finally I used natural instead of integer, as you instructed me .

Thanks

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