pack DSP OPMODE

[sgeorgi_sen]

Hi all,

I am using Vivado 2018.3 and stumbling on the following info:

INFO: [Synth 8-5842] Cannot pack DSP OPMODE registers because of constant '1' value. Packing the registers will cause simulation mismatch at initial cycle.

Vivado synthesis detects my dsp operations correctly, however timing is not met because OPMODE register is not used. During initial cycle there is no operation and simulation mismatch is irrelevant.

My question: Vivado detects the situation correctly. Is there an option to tell Vivado Synthesis to ignore simulation mismatch and pack OPMODE register into DSP anyway?

Thanks and regards,

Sebastian

[anusheel]

@sgeorgi_sen

Which device you are targetting to? Also, did you try use_dsp attribute, I doubt this will help but please give a try.

Can you show us your code here?

Thanks
Anusheel

[sgeorgi_sen]

@anusheel

Hi anusheel,

thanks for your reply. I am using Artix 7 and Vivado 2018.3. Please find attached an example file and synthesis report. DSP functions (such as Z-Mux and AddSub) are detected correctly. Only the OPMODE register is placed outside in a separate FF for simulation accuracy reasons.

As you already assumed, the usp_dsp attribute does not help - this was my first thought as well.

Help is appreciated.

Thanks and regards,

Sebastian